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Searched refs:DefR (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp441 unsigned DefR = Defs[i].Reg; in addInstrToLiveness() local
442 LiveInterval &LID = LIS->getInterval(DefR); in addInstrToLiveness()
443 DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI) in addInstrToLiveness()
473 MachineOperand ImpUse = MachineOperand::CreateReg(DefR, false, true); in addInstrToLiveness()
489 makeUndead(DefR, P->valno->def); in addInstrToLiveness()
497 if (!MI->readsRegister(DefR)) in addInstrToLiveness()
500 makeDefined(DefR, N->start, true); in addInstrToLiveness()
505 shrinkToUses(DefR, LID); in addInstrToLiveness()
555 unsigned DefR = Op.getReg(); in removeInstrFromLiveness() local
556 LiveInterval &LID = LIS->getInterval(DefR); in removeInstrFromLiveness()
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DHexagonGenMux.cpp69 unsigned DefR, PredR; member
75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1), in MuxInfo()
295 BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
DHexagonBitSimplify.cpp1175 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1176 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in computeUsedBits()
1178 Pending.push_back(DefR); in computeUsedBits()
2326 unsigned DefR; member
2333 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2334 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2352 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2390 unsigned DefR) const { in isBitShuffle()
2548 dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" in processLoop()
2576 unsigned DefR = Defs.find_first(); in processLoop() local
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DHexagonEarlyIfConv.cpp420 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local
421 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in isValid()
959 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
966 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
971 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()