Searched refs:DefReg (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 359 unsigned DefReg = NoRegister; in insertFaultingLoad() local
361 DefReg = LoadMI->defs().begin()->getReg(); in insertFaultingLoad()
366 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg) in insertFaultingLoad()
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| D | TailDuplication.cpp | 399 unsigned DefReg = MI->getOperand(0).getReg(); in ProcessPHI() local
403 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in ProcessPHI()
404 LocalVRMap.insert(std::make_pair(DefReg, SrcReg)); in ProcessPHI()
410 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in ProcessPHI()
411 AddSSAUpdateEntry(DefReg, NewDef, PredBB); in ProcessPHI()
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| D | LiveVariables.cpp | 218 unsigned DefReg = MO.getReg(); in FindLastPartialDef() local
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
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| D | TargetInstrInfo.cpp | 832 unsigned DefReg = MI->getOperand(0).getReg(); in isReallyTriviallyReMaterializableGeneric() local
838 if (TargetRegisterInfo::isVirtualRegister(DefReg) && in isReallyTriviallyReMaterializableGeneric()
839 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
890 if (MO.isDef() && Reg != DefReg) in isReallyTriviallyReMaterializableGeneric()
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| D | PHIElimination.cpp | 159 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local
160 if (MRI->use_nodbg_empty(DefReg)) { in runOnMachineFunction()
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| D | TwoAddressInstructionPass.cpp | 198 unsigned DefReg = 0; in sink3AddrInstruction() local
214 if (DefReg) in sink3AddrInstruction()
217 DefReg = MO.getReg(); in sink3AddrInstruction()
277 if (DefReg == MOReg) in sink3AddrInstruction()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.cpp | 355 int DefReg = 0; in loadImmediate() local
359 DefReg = MO.getReg(); in loadImmediate()
378 if (DefReg != Reg) { in loadImmediate()
393 if (DefReg!= SpReg) { in loadImmediate()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 665 unsigned DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
671 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
733 unsigned DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
735 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 224 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses() local
225 if (!TRI->isVirtualRegister(DefReg)) { in eraseInstrWithNoUses()
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| D | ARMLoadStoreOptimizer.cpp | 822 unsigned DefReg = MO.getReg(); in MergeOpsUpdate() local
824 if (std::find(ImpDefs.begin(), ImpDefs.end(), DefReg) != ImpDefs.end()) in MergeOpsUpdate()
827 if (MI->readsRegister(DefReg)) in MergeOpsUpdate()
829 ImpDefs.push_back(DefReg); in MergeOpsUpdate()
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