| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 516 FLOG, FLOG2, FLOG10, FEXP, FEXP2, enumerator
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| D | BasicTTIImpl.h | 630 ISD = ISD::FEXP2; in getIntrinsicInstrCost()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 169 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 85 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
1007 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
1855 case ISD::FEXP2: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 316 case ISD::FEXP2: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 81 case ISD::FEXP2: in ScalarizeVectorResult()
636 case ISD::FEXP2: in SplitVectorResult()
2094 case ISD::FEXP2: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 4070 case ISD::FEXP2: in ConvertNodeToLibcall()
4453 case ISD::FEXP2: { in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 4144 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); in expandExp2()
5876 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 85 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
348 setOperationAction(ISD::FEXP2, VT, Expand); in AMDGPUTargetLowering()
1044 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 844 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 313 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1871 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsMSAInstrInfo.td | 2039 // 1.0 when we only need to match ISD::FEXP2.
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 433 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 299 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in AArch64TargetLowering()
350 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand); in AArch64TargetLowering()
384 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); in AArch64TargetLowering()
656 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 510 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
528 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
545 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
669 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1760 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 460 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
703 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
749 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 677 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in X86TargetLowering()
741 setOperationAction(ISD::FEXP2, VT, Expand); in X86TargetLowering()
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