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Searched refs:FP_EXTEND (Results 1 – 22 of 22) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h477 FP_EXTEND, enumerator
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
63 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
DARMISelLowering.cpp575 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in ARMTargetLowering()
682 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in ARMTargetLowering()
6898 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp622 case ISD::FP_EXTEND: in isNegatibleForFree()
698 case ISD::FP_EXTEND: in GetNegatedExpression()
1423 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
7684 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7688 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7690 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7696 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7700 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7702 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7738 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
[all …]
DLegalizeFloatTypes.cpp94 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
443 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
641 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
739 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
1016 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1253 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1731 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1782 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
DLegalizeDAG.cpp460 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : in ExpandUnalignedLoad()
2580 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
3109 case ISD::FP_EXTEND: in ExpandNode()
3395 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4339 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4370 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4383 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4404 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4405 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4413 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp324 case ISD::FP_EXTEND: in LegalizeOp()
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
DSelectionDAGDumper.cpp251 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
DLegalizeVectorTypes.cpp88 case ISD::FP_EXTEND: in ScalarizeVectorResult()
643 case ISD::FP_EXTEND: in SplitVectorResult()
1444 case ISD::FP_EXTEND: in SplitVectorOperand()
2073 case ISD::FP_EXTEND: in WidenVectorResult()
2978 case ISD::FP_EXTEND: in WidenVectorOperand()
DSelectionDAG.cpp233 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
2946 case ISD::FP_EXTEND: { in getNode()
2992 case ISD::FP_EXTEND: in getNode()
3019 case ISD::FP_EXTEND: in getNode()
DSelectionDAGBuilder.cpp229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); in getCopyFromParts()
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); in getCopyToParts()
2584 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); in visitFPExt()
4839 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, in visitIntrinsicCall()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp551 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
552 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
635 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
DX86ISelDAGToDAG.cpp592 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
613 if (N->getOpcode() == ISD::FP_EXTEND) in PreprocessISelDAG()
DX86IntrinsicsInfo.h555 ISD::FP_EXTEND, 0),
557 ISD::FP_EXTEND, X86ISD::VFPEXT),
DX86ISelLowering.cpp946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in X86TargetLowering()
1382 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal); in X86TargetLowering()
2257 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
2334 } else if (Copy->getOpcode() != ISD::FP_EXTEND) in isUsedByReturnOnly()
12727 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in LowerUINT_TO_FP_i32()
13560 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); in LowerFCOPYSIGN()
20089 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
20273 case ISD::FP_EXTEND: { in ReplaceNodeResults()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp169 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
316 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
322 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
382 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
554 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1859 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
1875 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); in LowerVectorFP_TO_INT()
1893 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
2289 case ISD::FP_EXTEND: in LowerOperation()
3022 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp691 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
6047 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6050 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6059 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6067 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6080 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6083 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6090 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6096 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6102 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1700 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1728 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
2965 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1587 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td444 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1853 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); in HexagonTargetLowering()