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Searched refs:FP_ROUND (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dfp-double-rounding.ll26 ; Hack, to generate a precise FP_ROUND to double
/external/llvm/test/CodeGen/ARM/
Dneon_fpconv.ll3 ; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h459 FP_ROUND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp95 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
741 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
832 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
951 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1490 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1581 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
1596 Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, in ExpandFloatOp_FP_TO_SINT()
1885 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
DLegalizeVectorTypes.cpp56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
458 case ISD::FP_ROUND: in ScalarizeVectorOperand()
557 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
644 case ISD::FP_ROUND: in SplitVectorResult()
1190 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
1410 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
1927 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
1964 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
1965 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
DLegalizeDAG.cpp2577 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in ExpandLegalINT_TO_FP()
2670 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, in ExpandLegalINT_TO_FP()
3103 case ISD::FP_ROUND: in ExpandNode()
3406 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4340 TruncOp = ISD::FP_ROUND; in PromoteNode()
4348 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4408 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4417 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4434 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4456 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
DLegalizeVectorOps.cpp323 case ISD::FP_ROUND: in LegalizeOp()
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
DSelectionDAGDumper.cpp248 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
DDAGCombiner.cpp623 case ISD::FP_ROUND: in isNegatibleForFree()
703 case ISD::FP_ROUND: in GetNegatedExpression()
704 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
1421 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
8691 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
8695 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
8806 N1.getOpcode() == ISD::FP_ROUND) && in CanCombineFCOPYSIGN_EXTEND_ROUND()
9028 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); in visitFP_ROUND()
9035 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
9056 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
[all …]
DSelectionDAG.cpp3018 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
3571 case ISD::FP_ROUND: in getNode()
3786 if (Opcode == ISD::FP_ROUND) { in getNode()
DSelectionDAGBuilder.cpp226 ISD::FP_ROUND, DL, ValueVT, Val, in getCopyFromParts()
2574 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
4833 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, in visitIntrinsicCall()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp553 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
636 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
DX86ISelDAGToDAG.cpp592 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
624 if (N->getOpcode() == ISD::FP_ROUND) in PreprocessISelDAG()
DX86IntrinsicsInfo.h525 ISD::FP_ROUND, 0),
527 ISD::FP_ROUND, X86ISD::VFPROUND),
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
317 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
323 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
560 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
1925 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
1948 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2287 case ISD::FP_ROUND: in LowerOperation()
3720 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
4330 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1701 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1729 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1730 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
2966 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp168 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1841 case ISD::FP_ROUND: { in PerformDAGCombine()
DSIISelLowering.cpp201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
/external/llvm/test/CodeGen/AArch64/
Df16-instructions.ll732 ; Check that the FP promotion will use a truncating FP_ROUND, so we can fold
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1586 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp689 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
6345 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
6495 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
6570 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
10062 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
10414 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX in PerformDAGCombine()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp439 setTargetDAGCombine(ISD::FP_ROUND); in SystemZTargetLowering()
4780 if (Opcode == ISD::FP_ROUND) { in PerformDAGCombine()
4797 if (OtherRound.getOpcode() == ISD::FP_ROUND && in PerformDAGCombine()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td443 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1854 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); in HexagonTargetLowering()

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