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Searched refs:FP_TO_UINT (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp128 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
130 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
132 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
146 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
148 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
150 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
163 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
165 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
167 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
169 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
DARMISelLowering.cpp107 setOperationAction(ISD::FP_TO_UINT, VT, Custom); in addTypeForNEON()
112 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in addTypeForNEON()
571 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); in ARMTargetLowering()
626 setTargetDAGCombine(ISD::FP_TO_UINT); in ARMTargetLowering()
678 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in ARMTargetLowering()
680 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom); in ARMTargetLowering()
6847 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); in LowerOperation()
10585 case ISD::FP_TO_UINT: in PerformDAGCombine()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
261 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
267 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
269 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
274 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
281 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
DAArch64ISelLowering.cpp176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in AArch64TargetLowering()
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AArch64TargetLowering()
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); in AArch64TargetLowering()
485 setTargetDAGCombine(ISD::FP_TO_UINT); in AArch64TargetLowering()
557 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); in AArch64TargetLowering()
692 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom); in addTypeForNEON()
2330 case ISD::FP_TO_UINT: in LowerOperation()
9616 case ISD::FP_TO_UINT: in PerformDAGCombine()
9864 case ISD::FP_TO_UINT: in ReplaceNodeResults()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp542 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, in getCastInstrCost()
544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
545 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, in getCastInstrCost()
546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, in getCastInstrCost()
547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
604 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
605 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
606 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, in getCastInstrCost()
607 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, in getCastInstrCost()
[all …]
DX86IntrinsicsInfo.h605 ISD::FP_TO_UINT, 0),
607 ISD::FP_TO_UINT, 0),
609 ISD::FP_TO_UINT, ISD::FP_TO_UINT),
611 ISD::FP_TO_UINT, 0),
613 ISD::FP_TO_UINT, 0),
615 ISD::FP_TO_UINT, ISD::FP_TO_UINT),
629 ISD::FP_TO_UINT, 0),
631 ISD::FP_TO_UINT, 0),
633 ISD::FP_TO_UINT, ISD::FP_TO_UINT),
635 ISD::FP_TO_UINT, 0),
[all …]
DX86InstrFragmentsSIMD.td535 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
537 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
DX86ISelLowering.cpp229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); in X86TargetLowering()
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); in X86TargetLowering()
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); in X86TargetLowering()
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); in X86TargetLowering()
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); in X86TargetLowering()
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); in X86TargetLowering()
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); in X86TargetLowering()
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); in X86TargetLowering()
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); in X86TargetLowering()
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); in X86TargetLowering()
[all …]
/external/llvm/test/CodeGen/X86/
Davx-fp2int.ll3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
Dhalf.ll119 ; FP_TO_UINT is expanded using FP_TO_SINT
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h446 FP_TO_UINT, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp299 case ISD::FP_TO_UINT: in LegalizeOp()
391 case ISD::FP_TO_UINT: in Promote()
482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { in PromoteFP_TO_INT()
483 NewOpc = ISD::FP_TO_UINT; in PromoteFP_TO_INT()
DSelectionDAGDumper.cpp256 case ISD::FP_TO_UINT: return "fp_to_uint"; in getOperationName()
DLegalizeVectorTypes.cpp90 case ISD::FP_TO_UINT: in ScalarizeVectorResult()
441 case ISD::FP_TO_UINT: in ScalarizeVectorOperand()
646 case ISD::FP_TO_UINT: in SplitVectorResult()
1428 case ISD::FP_TO_UINT: in SplitVectorOperand()
2076 case ISD::FP_TO_UINT: in WidenVectorResult()
2980 case ISD::FP_TO_UINT: in WidenVectorOperand()
DLegalizeIntegerTypes.cpp110 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; in PromoteIntegerResult()
420 if (N->getOpcode() == ISD::FP_TO_UINT && in PromoteIntRes_FP_TO_XINT()
421 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
430 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? in PromoteIntRes_FP_TO_XINT()
1318 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; in ExpandIntegerResult()
DLegalizeFloatTypes.cpp743 case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break; in SoftenFloatOperand()
1492 case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break; in ExpandFloatOperand()
1730 case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break; in PromoteFloatOperand()
DLegalizeDAG.cpp2794 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2795 OpToUse = ISD::FP_TO_UINT; in PromoteLegalFP_TO_INT()
3155 case ISD::FP_TO_UINT: { in ExpandNode()
4266 case ISD::FP_TO_UINT: in PromoteNode()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AMDGPUTargetLowering()
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in AMDGPUTargetLowering()
635 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); in LowerOperation()
1555 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2241 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
2243 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP64_TO_INT()
DR600ISelLowering.cpp85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in R600TargetLowering()
873 case ISD::FP_TO_UINT: in ReplaceNodeResults()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp363 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
368 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
381 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
387 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
510 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
641 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
687 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand); in PPCTargetLowering()
737 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand); in PPCTargetLowering()
6237 (Op.getOpcode() == ISD::FP_TO_UINT || in canReuseLoadAddress()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1529 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1531 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
2938 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
3331 case ISD::FP_TO_UINT: in ReplaceNodeResults()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1833 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
1834 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); in HexagonTargetLowering()
1835 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); in HexagonTargetLowering()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1582 case FPToUI: return ISD::FP_TO_UINT; in InstructionOpcodeToISD()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); in addMSAIntType()
1908 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td450 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;

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