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Searched refs:FSEL (Results 1 – 8 of 8) sorted by relevance

/external/v8/src/ppc/
Dconstants-ppc.h272 FSEL = 23 << 1, // Floating Select enumerator
Ddisasm-ppc.cc921 case FSEL: { in DecodeExt4()
Dassembler-ppc.cc2214 emit(EXT4 | FSEL | frt.code() * B21 | fra.code() * B16 | frb.code() * B11 | in fsel()
Dsimulator-ppc.cc2765 case FSEL: { in ExecuteExt4()
/external/llvm/lib/Target/PowerPC/
DREADME.txt595 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
DPPCISelLowering.h33 FSEL, enumerator
DPPCISelLowering.cpp994 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
6048 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6051 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6060 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6068 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6081 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6084 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6091 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6097 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6103 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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DPPCInstrInfo.td108 def PPCfsel : SDNode<"PPCISD::FSEL",
2482 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid