| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| D | BasicTTIImpl.h | 621 ISD = ISD::FSIN; in getIntrinsicInstrCost()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 159 case ISD::FSIN: return "fsin"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 102 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1021 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
1864 case ISD::FSIN: in PromoteFloatResult()
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| D | LegalizeDAG.cpp | 2434 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2435 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3368 case ISD::FSIN: in ExpandNode()
4036 case ISD::FSIN: in ConvertNodeToLibcall()
4446 case ISD::FSIN: in PromoteNode()
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| D | LegalizeVectorOps.cpp | 308 case ISD::FSIN: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 93 case ISD::FSIN: in ScalarizeVectorResult()
649 case ISD::FSIN: in SplitVectorResult()
2103 case ISD::FSIN: in WidenVectorResult()
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| D | SelectionDAGBuilder.cpp | 4768 case Intrinsic::sin: Opcode = ISD::FSIN; break; in visitIntrinsicCall()
5813 if (visitUnaryFloatCall(I, ISD::FSIN)) in visitCall()
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| D | DAGCombiner.cpp | 624 case ISD::FSIN: in isNegatibleForFree()
699 case ISD::FSIN: in GetNegatedExpression()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 135 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 80 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
964 case ISD::FSIN: in LowerOperation()
1610 case ISD::FSIN: in LowerTrig()
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| D | R600ISelLowering.cpp | 65 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
600 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
971 case ISD::FSIN: in LowerTrig()
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| D | AMDGPUISelLowering.cpp | 359 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 160 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
265 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
266 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
295 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
341 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
373 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
545 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
648 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1616 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1699 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1758 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 765 #define FSIN CHOICE(fsin, fsin, fsin) macro
1486 #define FSIN fsin macro
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 502 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
520 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
537 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
661 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
919 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
920 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 431 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 359 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
360 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 161 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
167 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
461 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
695 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
741 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 547 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
550 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
577 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
589 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
605 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
606 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
655 setOperationAction(ISD::FSIN , MVT::f80, Expand); in X86TargetLowering()
704 setOperationAction(ISD::FSIN, VT, Expand); in X86TargetLowering()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1375 setOperationAction(ISD::FSIN, MVT::f32, Expand);
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 368 setOperationAction(ISD::FSIN, VT, Expand); in SystemZTargetLowering()
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