| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1034 case FSQRT: in check_double_guarded_arithmetic_op()
1139 case FSQRT: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1034 case FSQRT: in check_double_guarded_arithmetic_op()
1139 case FSQRT: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| D | BasicTTIImpl.h | 191 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
618 ISD = ISD::FSQRT; in getIntrinsicInstrCost()
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1330 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1331 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1332 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1334 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1335 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1336 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1651 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1652 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1722 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0),
1762 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
342 Opcode = ISD::FSQRT; break; in mightUseCTR()
|
| D | PPCISelLowering.cpp | 180 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
185 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
455 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
528 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
584 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
802 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
805 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
808 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
811 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
868 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
|
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 271 FSQRT = 22 << 1, // Floating Square Root enumerator
|
| D | disasm-ppc.cc | 917 case FSQRT: { in DecodeExt4()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 158 case ISD::FSQRT: return "fsqrt"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1022 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
1865 case ISD::FSQRT: in PromoteFloatResult()
|
| D | LegalizeVectorOps.cpp | 307 case ISD::FSQRT: in LegalizeOp()
|
| D | LegalizeVectorTypes.cpp | 94 case ISD::FSQRT: in ScalarizeVectorResult()
650 case ISD::FSQRT: in SplitVectorResult()
2104 case ISD::FSQRT: in WidenVectorResult()
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| D | DAGCombiner.cpp | 1415 case ISD::FSQRT: return visitFSQRT(N); in visit()
8679 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
8684 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8692 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8704 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8707 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
13831 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 546 // FDIV,FSQRT
548 // TODO: Specialize FSQRT for longer latency.
|
| D | AArch64ISelLowering.cpp | 162 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
297 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
343 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
375 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
547 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1048 FSQRT = FSQRT_s, enumerator
|
| D | disasm-arm64.cc | 973 FORMAT(FSQRT, "fsqrt"); in VisitFPDataProcessing1Source()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 356 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
|
| D | MipsSEISelLowering.cpp | 318 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1899 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1699 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1724 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
2961 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1154 FSQRT = FSQRT_s, enumerator
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1699 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1758 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 767 #define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) macro
1488 #define FSQRT fsqrt macro
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 430 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
|