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Searched refs:Low (Results 1 – 25 of 138) sorted by relevance

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/external/llvm/lib/Transforms/Utils/
DLowerSwitch.cpp36 int64_t Low, High; member
49 return I != Ranges.end() && I->Low <= R.Low; in IsInRanges()
69 ConstantInt* Low; member
74 : Low(low), High(high), BB(bb) {} in CaseRange()
98 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); in operator ()()
151 O << *B->Low << " -" << *B->High; in operator <<()
218 if (Begin->Low == LowerBound && Begin->High == UpperBound) { in switchConvert()
237 << Pivot.Low->getValue() in switchConvert()
244 ConstantInt *NewLowerBound = Pivot.Low; in switchConvert()
281 Val, Pivot.Low, "Pivot"); in switchConvert()
[all …]
/external/lzma/CS/7zip/Compress/RangeCoder/
DRangeCoder.cs11 public UInt64 Low; field in SevenZip.Compression.RangeCoder.Encoder
32 Low = 0; in Init()
56 Low += start * (Range /= total); in Encode()
67 if ((uint)Low < (uint)0xFF000000 || (uint)(Low >> 32) == 1) in ShiftLow()
72 Stream.WriteByte((byte)(temp + (Low >> 32))); in ShiftLow()
76 _cache = (byte)(((uint)Low) >> 24); in ShiftLow()
79 Low = ((uint)Low) << 8; in ShiftLow()
88 Low += Range; in EncodeDirectBits()
104 Low += newBound; in EncodeBit()
/external/lzma/CPP/7zip/Compress/
DRangeCoder.h21 UInt64 Low;
30 Low = 0; in Init()
47 Low += start * (Range /= total); in Encode()
58 if ((UInt32)Low < (UInt32)0xFF000000 || (unsigned)(Low >> 32) != 0) in ShiftLow()
63 Stream.WriteByte((Byte)(temp + (Byte)(Low >> 32))); in ShiftLow()
67 _cache = (Byte)((UInt32)Low >> 24); in ShiftLow()
70 Low = (UInt32)Low << 8; in ShiftLow()
78 Low += Range & (0 - ((value >> numBits) & 1)); in EncodeDirectBits()
94 Low += newBound; in EncodeBit()
/external/lzma/Java/SevenZip/Compression/RangeCoder/
DEncoder.java14 long Low; field in Encoder
34 Low = 0; in Init()
53 int LowHi = (int)(Low >>> 32); in ShiftLow()
54 if (LowHi != 0 || Low < 0xFF000000L) in ShiftLow()
64 _cache = (((int)Low) >>> 24); in ShiftLow()
67 Low = (Low & 0xFFFFFF) << 8; in ShiftLow()
76 Low += Range; in EncodeDirectBits()
113 Low += (newBound & 0xFFFFFFFFL); in Encode()
/external/gemmlowp/meta/generators/
Dqnt_Nx8_neon.py41 [emitter.AllLanes(registers.Low(register)),
117 emitter.EmitVQmovun('s16', registers.Low(lane_temp), lane_temp)
134 [registers.Low(lane.load_1),
136 registers.Low(lane.load_2),
145 quantize_setup.append([lane.load_1, lane.offset, registers.Low(lane_temp)])
158 registers.Low(lane_temp),
170 emitter.Lane(registers.Low(lane.load_1), 0),
175 registers.Low(lane.load_1),
180 registers.Low(lane.load_1),
189 [registers.Low(lane.load_1),
[all …]
Dmul_Nx8_Mx8_neon.py42 lanes.AddLane(registers.Low(quad_register))
197 registers.Low(values), 0))
199 registers.Low(values), 1))
221 register = registers.Low(aggregators[row])
225 register = registers.Low(aggregators[row * 2])
227 registers.Low(aggregators[row * 2 + 1]))
231 emitter.EmitVPadd('u32', registers.Low(register), registers.Low(register),
232 registers.Low(aggregators[row * 3 + 1]))
234 registers.Low(aggregators[row * 3 + 2]),
235 registers.Low(aggregators[row * 3 + 2]))
[all …]
Dneon_emitter.py30 def Low(register): function
93 def Low(self, register): member in NeonRegisters
94 return Low(register)
/external/lzma/C/
DPpmd7Enc.c13 p->Low = 0; in Ppmd7z_RangeEnc_Init()
21 if ((UInt32)p->Low < (UInt32)0xFF000000 || (unsigned)(p->Low >> 32) != 0) in RangeEnc_ShiftLow()
26 p->Stream->Write(p->Stream, (Byte)(temp + (Byte)(p->Low >> 32))); in RangeEnc_ShiftLow()
30 p->Cache = (Byte)((UInt32)p->Low >> 24); in RangeEnc_ShiftLow()
33 p->Low = (UInt32)p->Low << 8; in RangeEnc_ShiftLow()
38 p->Low += start * (p->Range /= total); in RangeEnc_Encode()
60 p->Low += newBound; in RangeEnc_EncodeBit_1()
/external/llvm/lib/Transforms/IPO/
DArgumentPromotion.cpp378 std::set<ArgPromotion::IndicesVector>::iterator Low; in PrefixIn() local
379 Low = Set.upper_bound(Indices); in PrefixIn()
380 if (Low != Set.begin()) in PrefixIn()
381 Low--; in PrefixIn()
387 return Low != Set.end() && IsPrefix(*Low, Indices); in PrefixIn()
397 std::set<ArgPromotion::IndicesVector>::iterator Low; in MarkIndicesSafe() local
398 Low = Safe.upper_bound(ToMark); in MarkIndicesSafe()
400 if (Low != Safe.begin()) in MarkIndicesSafe()
401 Low--; in MarkIndicesSafe()
405 if (Low != Safe.end()) { in MarkIndicesSafe()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.h151 const ConstantInt *Low, *High; member
159 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High, in range()
163 C.Low = Low; in range()
170 static CaseCluster jumpTable(const ConstantInt *Low, in jumpTable()
175 C.Low = Low; in jumpTable()
182 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High, in bitTests()
186 C.Low = Low; in bitTests()
324 bool rangeFitsInWord(const APInt &Low, const APInt &High);
329 const APInt &Low, const APInt &High);
/external/clang/test/Index/
Dcomplete-type-factors.m8 Low,
32 [A method:Red priority:Low];
44 // CHECK-CC1: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (32)
59 // CHECK-CC2: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (65)
75 // CHECK-CC3: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (16)
91 // CHECK-CC4: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (65)
109 // CHECK-CC6: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (65)
123 // CHECK-CC7: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (65)
135 // CHECK-CC8: EnumConstantDecl:{ResultType enum Priority}{TypedText Low} (16)
/external/llvm/test/Analysis/LoopAccessAnalysis/
Dnumber-of-memchecks.ll98 ; CHECK-NEXT: (Low: %c High: (78 + %c))
102 ; CHECK-NEXT: (Low: %a High: (40 + %a))
106 ; CHECK-NEXT: (Low: %b High: (38 + %b))
170 ; CHECK-NEXT: (Low: %c High: (78 + %c))
174 ; CHECK-NEXT: (Low: %a High: (40 + %a))
178 ; CHECK-NEXT: (Low: %b High: (38 + %b))
249 ; CHECK-NEXT: (Low: ((2 * %offset) + %a) High: (9998 + (2 * %offset) + %a))
252 ; CHECK-NEXT: (Low: %a High: (9998 + %a))
255 ; CHECK-NEXT: (Low: (20000 + %a) High: (29998 + %a))
Dreverse-memcheck-bounds.ll18 ; CHECK: (Low: (20000 + %a) High: (60000 + %a))
60 ; CHECK: Low: (-1 + (-1 * ((-60001 + (-1 * %a)) umax (-60001 + (40000 * %step) + (-1 * %a)))))
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp401 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() local
404 TmpInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
486 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() local
489 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
498 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() local
501 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
511 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction() local
514 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
DHexagonBitSimplify.cpp1674 bool Low; // Low/High halfword. member
1716 bool Low = false; in matchHalf() local
1757 Low = true; in matchHalf()
1761 Low = false; in matchHalf()
1765 Low = true; in matchHalf()
1769 Low = false; in matchHalf()
1777 RH.Low = Low; in matchHalf()
1799 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) in matchPackhl()
1801 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) in matchPackhl()
1834 if (H.Low) in genStoreUpperHalf()
[all …]
/external/boringssl/src/util/
Ddoc.config4 "Name": "Low-level infrastructure",
22 "Name": "Low-level crypto primitives",
/external/llvm/unittests/ADT/
DVariadicFunctionTest.cpp88 void CountInRangeImpl(int *NumInRange, int Low, int High, in CountInRangeImpl() argument
92 if (Low <= *Args[i] && *Args[i] <= High) in CountInRangeImpl()
/external/libvpx/libvpx/test/
Dregister_state_check.h43 return (lhs.Low == rhs.Low && lhs.High == rhs.High);
/external/skia/src/sfnt/
DSkPanose.h94 ((Low, 4))
281 ((Low, 4))
353 ((Low, 3))
422 ((Low, 4))
/external/libmtp/
DChangeLog241 2009-05-03 Richard Low <richard@wentnet.com>
257 2009-05-02 Richard Low <richard@wentnet.com>
261 2009-04-18 Richard Low <richard@wentnet.com>
265 2009-04-11 Richard Low <richard@wentnet.com>
463 2008-09-26 Richard Low <richard@wentnet.com>
484 2008-09-23 Richard Low <richard@wentnet.com>
519 2008-09-07 Richard Low <richard@wentnet.com>
744 2008-05-18 Richard Low <richard@wentnet.com>
829 2008-02-24 Richard Low <richard@wentnet.com>
891 2008-01-21 Richard Low <richard@wentnet.com>
[all …]
/external/llvm/test/CodeGen/X86/
Dload-slice.ll14 ; Low High
16 ; Low slice starts at 0 (base) and is 8-bytes aligned.
88 ; Low High
90 ; Low slice starts at 0 (base) and is 8-bytes aligned.
/external/icu/icu4c/source/data/lang/
Den_GB.txt15 nds_NL{"West Low German"}
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrAtomics.td36 // Low-level exclusive operations
/external/llvm/
DREADME.txt1 Low Level Virtual Machine (LLVM)
/external/autotest/client/site_tests/audio_Microphone/
Dcontrol11 Low latency capturing should work fine with low CPU usage.

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