Searched refs:MFVSRWZ (Results 1 – 5 of 5) sorted by relevance
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 197 MFVSRWZ = 115 << 1, // Move From VSR Word And Zero enumerator
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| D | disasm-ppc.cc | 855 case MFVSRWZ: { in DecodeExt2()
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| D | assembler-ppc.cc | 1865 emit(EXT2 | MFVSRWZ | src.code() * B21 | dst.code() * B16); in mffprwz()
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| D | simulator-ppc.cc | 2103 case MFVSRWZ: { in ExecuteExt2_9bit_part1()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrVSX.td | 1225 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1288 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 2), sub_64));
1289 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));
1290 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG
1292 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));
1767 (i32 (MFVSRWZ (EXTRACT_SUBREG
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