| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 896 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1401 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 578 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
581 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
584 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
587 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
592 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
603 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
610 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
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| D | X86InstrSystem.td | 245 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
247 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
249 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
562 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
565 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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| D | X86InstrFPStack.td | 279 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;
280 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">;
281 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">;
387 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op),
395 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op),
542 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
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| D | X86InstrArithmetic.td | 501 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
506 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
510 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
514 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
1193 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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| D | X86InstrInfo.td | 2188 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2189 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2404 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2407 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
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| D | X86InstrFormats.td | 30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| D | X86InstrAVX512.td | 4095 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
717 case X86Local::MRM1r: in emitInstructionSpecifier()
853 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1820 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
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