Searched refs:NumLanes (Results 1 – 9 of 9) sorted by relevance
/external/llvm/lib/Target/X86/Utils/ |
D | X86ShuffleDecode.cpp | 86 unsigned NumLanes = VectorSizeInBits / 128; in DecodeMOVDDUPMask() local 87 unsigned NumLaneElts = NumElts / NumLanes; in DecodeMOVDDUPMask() 99 unsigned NumLanes = VectorSizeInBits / 128; in DecodePSLLDQMask() local 100 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSLLDQMask() 113 unsigned NumLanes = VectorSizeInBits / 128; in DecodePSRLDQMask() local 114 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSRLDQMask() 130 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePALIGNRMask() local 131 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask() 149 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePSHUFMask() local 150 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask() [all …]
|
/external/llvm/lib/IR/ |
D | AutoUpgrade.cpp | 289 Value *Op, unsigned NumLanes, in UpgradeX86PSLLDQIntrinsics() argument 292 unsigned NumElts = NumLanes * 16; in UpgradeX86PSLLDQIntrinsics() 319 VectorType::get(Type::getInt64Ty(C), 2*NumLanes), in UpgradeX86PSLLDQIntrinsics() 326 Value *Op, unsigned NumLanes, in UpgradeX86PSRLDQIntrinsics() argument 329 unsigned NumElts = NumLanes * 16; in UpgradeX86PSRLDQIntrinsics() 356 VectorType::get(Type::getInt64Ty(C), 2*NumLanes), in UpgradeX86PSRLDQIntrinsics()
|
/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.h | 142 template <unsigned NumLanes, char LaneKind>
|
D | AArch64InstPrinter.cpp | 1285 template <unsigned NumLanes, char LaneKind> 1290 if (NumLanes) in printTypedVectorList() 1291 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
|
/external/clang/utils/TableGen/ |
D | NeonEmitter.cpp | 705 unsigned NumLanes; in fromTypedefName() local 706 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName() 708 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
|
/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 7295 int NumLanes = VT.getSizeInBits() / 128; in lowerVectorShuffleAsByteRotate() local 7296 int NumLaneElts = NumElts / NumLanes; in lowerVectorShuffleAsByteRotate() 7370 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes); in lowerVectorShuffleAsByteRotate() 7794 int NumLanes = Bits / 128; in lowerVectorShuffleAsZeroOrAnyExtend() local 7796 int NumEltsPerLane = NumElements / NumLanes; in lowerVectorShuffleAsZeroOrAnyExtend() 10296 int NumLanes = Size / LaneSize; in lowerVectorShuffleByMerging128BitLanes() local 10297 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles."); in lowerVectorShuffleByMerging128BitLanes() 10302 Lanes.resize(NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes() 10333 LaneMask.resize(NumLanes * 2, -1); in lowerVectorShuffleByMerging128BitLanes() 10334 for (int i = 0; i < NumLanes; ++i) in lowerVectorShuffleByMerging128BitLanes() [all …]
|
/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 9998 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local 9999 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVCVTCombine() 10018 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine() 10056 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local 10057 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVDIVCombine() 10076 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 7599 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local 7600 switch (NumLanes) { in performFpToIntCombine() 7664 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local 7665 switch (NumLanes) { in performFDivCombine()
|
/external/clang/lib/CodeGen/ |
D | CGBuiltin.cpp | 6339 unsigned NumLanes = NumElts / 16; in EmitX86BuiltinExpr() local 6340 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
|