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Searched refs:OFFSET (Results 1 – 25 of 80) sorted by relevance

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/external/mesa3d/src/mesa/x86/
Dgen_matypes.c69 #define OFFSET( s, t, m ) \ macro
96 OFFSET( "CTX_DRIVER_CTX ", struct gl_context, DriverCtx ); in main()
98 OFFSET( "CTX_LIGHT_ENABLED ", struct gl_context, Light.Enabled ); in main()
99 OFFSET( "CTX_LIGHT_SHADE_MODEL ", struct gl_context, Light.ShadeModel ); in main()
100 OFFSET( "CTX_LIGHT_COLOR_MAT_FACE ", struct gl_context, Light.ColorMaterialFace ); in main()
101 OFFSET( "CTX_LIGHT_COLOR_MAT_MODE ", struct gl_context, Light.ColorMaterialMode ); in main()
102 OFFSET( "CTX_LIGHT_COLOR_MAT_MASK ", struct gl_context, Light._ColorMaterialBitmask ); in main()
103 OFFSET( "CTX_LIGHT_COLOR_MAT_ENABLED ", struct gl_context, Light.ColorMaterialEnabled ); in main()
104 OFFSET( "CTX_LIGHT_ENABLED_LIST ", struct gl_context, Light.EnabledList ); in main()
105 OFFSET( "CTX_LIGHT_NEED_VERTS ", struct gl_context, Light._NeedVertices ); in main()
[all …]
/external/libunwind/src/ia64/
Dmk_Gcursor_i.c36 #define OFFSET(sym, offset) \ macro
42 OFFSET("IP_OFF", offsetof (struct cursor, ip)); in main()
43 OFFSET("PR_OFF", offsetof (struct cursor, pr)); in main()
44 OFFSET("BSP_OFF", offsetof (struct cursor, bsp)); in main()
45 OFFSET("PSP_OFF", offsetof (struct cursor, psp)); in main()
46 OFFSET("PFS_LOC_OFF", offsetof (struct cursor, loc[IA64_REG_PFS])); in main()
47 OFFSET("RNAT_LOC_OFF", offsetof (struct cursor, loc[IA64_REG_RNAT])); in main()
48 OFFSET("UNAT_LOC_OFF", offsetof (struct cursor, loc[IA64_REG_UNAT])); in main()
49 OFFSET("LC_LOC_OFF", offsetof (struct cursor, loc[IA64_REG_LC])); in main()
50 OFFSET("FPSR_LOC_OFF", offsetof (struct cursor, loc[IA64_REG_FPSR])); in main()
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/external/elfutils/tests/
Drun-readelf-vmcoreinfo.sh73 OFFSET(mem_section.section_mem_map)=0
80 OFFSET(page.flags)=0
81 OFFSET(page._count)=8
82 OFFSET(page.mapping)=24
83 OFFSET(page.lru)=40
84 OFFSET(pglist_data.node_zones)=0
85 OFFSET(pglist_data.nr_zones)=81472
86 OFFSET(pglist_data.node_start_pfn)=81496
87 OFFSET(pglist_data.node_spanned_pages)=81512
88 OFFSET(pglist_data.node_id)=81520
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/external/libunwind/src/mips/
Dgetcontext-android.S32 # define OFFSET 4 macro
34 # define OFFSET 0 macro
37 sw $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X + OFFSET) ($4); \
39 sw $1, (LINUX_UC_MCONTEXT_GREGS + 8 * X + 4 - OFFSET) ($4)
42 sw $31, (LINUX_UC_MCONTEXT_PC + OFFSET) ($4); \
44 sw $1, (LINUX_UC_MCONTEXT_PC + 4 - OFFSET) ($4)
Dgetcontext.S33 # define OFFSET 4 macro
35 # define OFFSET 0 macro
38 sw $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X + OFFSET) ($4); \
40 sw $1, (LINUX_UC_MCONTEXT_GREGS + 8 * X + 4 - OFFSET) ($4)
43 sw $31, (LINUX_UC_MCONTEXT_PC + OFFSET) ($4); \
45 sw $1, (LINUX_UC_MCONTEXT_PC + 4 - OFFSET) ($4)
/external/fec/
Dpeaktest.c10 #define OFFSET 1 macro
30 rresult = peakval_port(&samples[OFFSET],NSAMP-OFFSET); in main()
31 result = peakval(&samples[OFFSET],NSAMP-OFFSET); in main()
Dsqtest.c8 #define OFFSET 1 macro
23 rresult = sumsq_wq(&samples[OFFSET],NSAMP-OFFSET); in main()
24 result = sumsq_wq(&samples[OFFSET],NSAMP-OFFSET); in main()
Dvtest615.c34 #define OFFSET (127.5) macro
122 symbols[6*i+0] = addnoise(parity(sr & V615POLYA),gain,Gain,OFFSET,CLIP);
123 symbols[6*i+1] = addnoise(parity(sr & V615POLYB),gain,Gain,OFFSET,CLIP);
124 symbols[6*i+2] = addnoise(parity(sr & V615POLYC),gain,Gain,OFFSET,CLIP);
125 symbols[6*i+3] = addnoise(parity(sr & V615POLYD),gain,Gain,OFFSET,CLIP);
126 symbols[6*i+4] = addnoise(parity(sr & V615POLYE),gain,Gain,OFFSET,CLIP);
127 symbols[6*i+5] = addnoise(parity(sr & V615POLYF),gain,Gain,OFFSET,CLIP);
/external/clang/test/CodeGenObjC/
Darc-property.m26 // CHECK: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test1.pointer"
28 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 [[OFFSET]]
36 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test1.pointer"
39 // CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T2]], i1 …
61 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
63 // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8, i8* [[T2]], i64 [[OFFSET]]
69 // CHECK: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
70 // CHECK-NEXT: [[T0:%.*]] = tail call i8* @objc_getProperty(i8* {{.*}}, i8* {{.*}}, i64 [[OFFSET]],…
75 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
77 // CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T1]], i1 …
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-conversion-p5.ll10 ; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
11 ; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
22 ; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
23 ; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
35 ; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
36 ; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
48 ; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
49 ; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
Dmemcpy-vec.ll17 ; PWR7-DAG: li [[OFFSET:[0-9]+]], 16
18 ; PWR7-DAG: lxvd2x [[TMP0:[0-9]+]], 4, [[OFFSET]]
/external/llvm/test/CodeGen/AMDGPU/
Dsmrd.ll31 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
32 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
61 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
62 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
75 ; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
76 ; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
117 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
118 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
132 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
133 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
[all …]
Dscratch-buffer.ll14 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0{{$}}
15 ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen
16 ; GCN: v_mov_b32_e32 [[OFFSET]], 0x8000
17 ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
54 ; GCN: v_add_i32_e32 [[OFFSET:v[0-9]+]], vcc, 0x8000
55 ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
Dcgp-addressing-modes.ll289 ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x400
291 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
376 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc{{$}}
377 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
411 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}}
412 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
416 ; VI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}}
417 ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
/external/libopus/silk/
Dgain_quant.c34 #define OFFSET ( ( MIN_QGAIN_DB * 128 ) / 6 + 16 * 128 ) macro
51 ind[ k ] = silk_SMULWB( SCALE_Q16, silk_lin2log( gain_Q16[ k ] ) - OFFSET ); in silk_gains_quant()
88 …gain_Q16[ k ] = silk_log2lin( silk_min_32( silk_SMULWB( INV_SCALE_Q16, *prev_ind ) + OFFSET, 3967 … in silk_gains_quant()
122 …gain_Q16[ k ] = silk_log2lin( silk_min_32( silk_SMULWB( INV_SCALE_Q16, *prev_ind ) + OFFSET, 3967 … in silk_gains_dequant()
/external/skia/src/gpu/
DGrProgramDesc.h98 template<typename T, size_t OFFSET> T* atOffset() { in atOffset()
99 return reinterpret_cast<T*>(reinterpret_cast<intptr_t>(fKey.begin()) + OFFSET); in atOffset()
102 template<typename T, size_t OFFSET> const T* atOffset() const { in atOffset()
103 return reinterpret_cast<const T*>(reinterpret_cast<intptr_t>(fKey.begin()) + OFFSET); in atOffset()
/external/llvm/test/CodeGen/X86/
Dextractelement-legalization-cycle.ll12 ; CHECK: movaps %xmm0, -[[OFFSET:[0-9]+]](%rsp)
13 ; CHECK: movss -[[OFFSET]](%rsp,{{.*}}), %xmm0 {{.*}}
/external/llvm/test/CodeGen/Mips/
Dinlineasmmemop.ll10 ; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
14 ; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
/external/icu/icu4c/source/test/intltest/
Dtzfmttst.cpp855 const int32_t OFFSET[] = { in TestISOFormat() local
960 for (uint32_t i = 0; i < sizeof(OFFSET)/sizeof(OFFSET[0]); i++) { in TestISOFormat()
961 …SimpleTimeZone* tz = new SimpleTimeZone(OFFSET[i], UnicodeString("Zone Offset:") + OFFSET[i] + "ms… in TestISOFormat()
970 … errln((UnicodeString)"FAIL: pattern=" + PATTERN[j] + ", offset=" + OFFSET[i] + " -> " in TestISOFormat()
978 … errln((UnicodeString)"FAIL: Non-Empty result for pattern=" + PATTERN[j] + ", offset=" + OFFSET[i] in TestISOFormat()
1009 int32_t adjustedOffset = OFFSET[i] / MIN_OFFSET_UNIT[j] * MIN_OFFSET_UNIT[j]; in TestISOFormat()
/external/llvm/test/CodeGen/SystemZ/
Dframe-16.ll224 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
227 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
231 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
234 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
260 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
263 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
269 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
272 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
Dframe-13.ll213 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
216 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
220 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
223 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
251 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
254 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td186 bits<12> OFFSET;
199 let Inst{11-0} = OFFSET;
225 bits<12> OFFSET;
237 let Inst{11-0} = OFFSET;
263 bits<8> OFFSET = PTR{7-0};
267 let Inst{7-0} = OFFSET;
/external/compiler-rt/test/msan/
Dchained_origin_memcpy.cc46 return yy[idx + OFFSET]; in main()
/external/llvm/test/Object/
Dcorrupt.test63 RUN: FileCheck --check-prefix=DYN-TABLE-OFFSET %s
65 DYN-TABLE-OFFSET: Invalid data was encountered while parsing the file.
/external/llvm/test/CodeGen/Generic/
D2002-04-16-StackFrameSizeAlignment.ll4 ; Sparc.cpp:91: failed assertion `(offset - OFFSET) % getStackFrameSizeAlignment() == 0'

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