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Searched refs:Orders (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp702 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
719 Orders.push_back(std::make_pair(DVOrder, DbgMI)); in ProcessSDDbgValues()
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSourceNode()
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr)); in ProcessSourceNode()
753 Orders.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos()))); in ProcessSourceNode()
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
[all …]
/external/llvm/utils/TableGen/
DCodeGenRegisters.h270 std::vector<SmallVector<Record*, 16> > Orders; variable
384 return Orders[No];
388 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
DCodeGenRegisters.cpp679 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
683 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
694 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
758 Orders.resize(Super.Orders.size()); in inheritProperties()
759 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
760 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
761 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
762 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
/external/chromium-trace/catapult/third_party/gsutil/third_party/boto/boto/mws/
Dresponse.py643 Orders = Element(Order=ElementList(Order)) variable in ListOrdersResult
/external/clang/lib/CodeGen/
DCGBuiltin.cpp1362 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1376 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
1428 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
1438 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()