| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 132 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
134 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
137 ; HAS-SEB-SEH: seb $2, $[[R16]]
172 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
174 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
177 ; HAS-SEB-SEH:seb $2, $[[R16]]
213 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
215 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
218 ; HAS-SEB-SEH: seb $2, $[[R16]]
252 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
[all …]
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 61 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
98 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
141 R28, R29, R17, R16
147 add R23, R22, R21, R20, R19, R18, R17, R16
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 52 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg()
81 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
|
| D | HexagonFrameLowering.h | 61 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
|
| D | HexagonFrameLowering.cpp | 658 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, in insertCFIInstructionsAt()
821 for (unsigned R = Hexagon::R16; R <= MaxReg; ++R) { in addCalleeSaveRegistersAsImpOperand()
|
| D | HexagonRegisterInfo.td | 105 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
|
| D | HexagonInstrInfo.cpp | 109 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
|
| /external/llvm/test/Transforms/LowerBitSets/ |
| D | simple.ll | 88 ; CHECK: [[R16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[R11]], {{%[^ ]*}} ]
94 ; CHECK: ret i1 [[R16]]
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 168 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 212 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
221 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
|
| D | PPCFrameLowering.cpp | 153 {PPC::R16, -64}, in getCalleeSavedSpillSlots()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 38 def R16 : AMDILReg<16, "r16">, DwarfRegNum<[16]>;
|
| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 36 def R16 : RegisterClass;
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 548 Register = Hexagon::R16; in compoundRegisterMap()
|
| D | HexagonMCInstrInfo.cpp | 470 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); in isIntRegForSubInst()
|
| D | HexagonMCDuplexInfo.cpp | 670 case Hexagon::R16: in addOps()
|
| /external/valgrind/VEX/orig_ppc32/ |
| D | date.orig | 6156 8: GETL R16, t6
6185 29: PUTL t22, R16
6196 36: GETL R16, t28
7277 0: GETL R16, t0
10437 21: GETL R16, t16
10445 27: PUTL t20, R16
11271 17: GETL R16, t16
11285 27: PUTL t24, R16
11296 34: GETL R16, t30
11311 45: PUTL t38, R16
[all …]
|
| D | return0.orig | 6156 8: GETL R16, t6
6185 29: PUTL t22, R16
6196 36: GETL R16, t28
7277 0: GETL R16, t0
10274 21: GETL R16, t16
10282 27: PUTL t20, R16
11108 17: GETL R16, t16
11122 27: PUTL t24, R16
11133 34: GETL R16, t30
11148 45: PUTL t38, R16
[all …]
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
|
| /external/libpng/contrib/libtests/ |
| D | pngvalid.c | 312 #define R16(this) r16(&(this), (sizeof (this))/(sizeof (png_uint_16))) macro
3336 R16(tRNS.red); in set_random_tRNS()
3337 R16(tRNS.green); in set_random_tRNS()
3346 R16(tRNS.red); in set_random_tRNS()
3354 R16(tRNS.gray); in set_random_tRNS()
|
| /external/opencv3/modules/core/src/ |
| D | gl_core_3_1.hpp | 755 R16 = 0x822A, enumerator
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 496 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
|