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Searched refs:R700 (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DR700Instructions.td1 //===-- R700Instructions.td - R700 Instruction defs -------*- tablegen -*-===//
11 // - Available to R700 and newer VLIW4/VLIW5 GPUs
12 // - Available only on R700 family GPUs.
16 def isR700 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::R700">;
DAMDGPUSubtarget.h39 R700, enumerator
DProcessors.td32 // R700
DAMDGPU.td216 def FeatureR700 : SubtargetFeatureGeneration<"R700",
DR600ControlFlowFinalizer.cpp122 if (ST->getGeneration() <= AMDGPUSubtarget::R700) { in getSubEntrySize()
DR600Instructions.td338 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
676 // Common Instructions R600, R700, Evergreen, Cayman
1157 // R600 / R700 Instructions
DR600InstrInfo.cpp1259 if (ST.getGeneration() <= AMDGPUSubtarget::R700) in buildSlotOfVectorInstruction()
DR600ISelLowering.cpp980 if (Gen >= AMDGPUSubtarget::R700) in LowerTrig()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_pipe.c250 case R700: in r600_create_context()
256 rctx->custom_blend_resolve = rctx->chip_class == R700 ? r700_create_resolve_blend(rctx) in r600_create_context()
869 if (rscreen->chip_class <= R700) { in r600_init_tiling()
878 if (rscreen->chip_class <= R700) { in r600_init_tiling()
928 rscreen->chip_class = R700; in r600_screen_create()
942 case R700: in r600_screen_create()
Dr600_asm.c43 case R700: in r600_bytecode_get_num_operands()
346 case R700: in is_alu_once_inst()
427 case R700: in is_alu_reduction_inst()
448 case R700: in is_alu_cube_inst()
463 case R700: in is_alu_mova_inst()
497 case R700: in is_alu_vec_unit_inst()
559 case R700: in is_alu_trans_unit_inst()
594 case R700: in is_nop_inst()
695 if (bc->chip_class >= R700) { in reserve_cfile()
1563 case R700: in r600_bytecode_num_tex_and_vtx_instructions()
[all …]
Dr600.h70 R700, enumerator
Dr600_state_common.c186 if (rctx->chip_class <= R700 && in r600_bind_blend_state_internal()
431 …if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cub… in r600_bind_samplers()
645 if (rctx->chip_class <= R700 && in r600_set_sampler_views()
830 if (rctx->chip_class <= R700) { in r600_bind_ps_shader()
Dr600_state.c927 if (rctx->chip_class >= R700) { in r600_create_rs_state()
1797 if (rctx->chip_class >= R700) { in r600_emit_db_misc_state()
2340 if (rctx->chip_class >= R700) { in r600_init_atom_start_cs()
2425 if (rctx->chip_class >= R700) { in r600_init_atom_start_cs()
2450 if (rctx->chip_class == R700 && rctx->screen->has_streamout) in r600_init_atom_start_cs()
Dr600_hw_context.c954 if (ctx->chip_class <= R700) { in r600_context_flush()
983 if (ctx->chip_class <= R700) { in r600_context_flush()
Dr600_texture.c288 if (rscreen->chip_class <= R700) { in r600_texture_get_fmask_info()
/external/mesa3d/src/gallium/drivers/radeon/
DR600Instructions.td238 // Common Instructions R600, R700, Evergreen, Cayman
719 // R600 / R700 Instructions
761 // Helper pattern for normalizing inputs to triginomic instructions for R700+
769 // R700 Only instructions
776 // R700 normalizes inputs to SIN/COS the same as EG
/external/llvm/docs/
DCompilerWriterInfo.rst77 * `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Se…