| /external/llvm/test/CodeGen/X86/ |
| D | segmented-stacks-dynamic.ll | 56 ; X64: movq %rsp, %[[RDI:rdi|rax]]
57 ; X64: subq %{{.*}}, %[[RDI]]
58 ; X64-NEXT: cmpq %[[RDI]], %fs:112
60 ; X64: movq %[[RDI]], %rsp
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| D | maskmovdqu.ll | 2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,-avx | grep -i RDI
4 ; RUN: llc < %s -march=x86-64 -mattr=+avx | grep -i RDI
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| D | or-address.ll | 50 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
51 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
53 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
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| D | 2010-04-08-CoalescerBug.ll | 5 ; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>
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| D | critical-anti-dep-breaker.ll | 5 ; This test case expects such an instruction to appear as a comment with def info for RDI.
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| D | 2010-06-01-DeadArg-DbgInfo.ll | 11 ;CHECK: DEBUG_VALUE: baz:this <- %RDI{{$}}
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| D | ghc-cc64.ll | 11 @r4 = external global i64 ; assigned to register: RDI
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| /external/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 57 const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
225 const unsigned ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
251 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemcpy()
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| D | X86RegisterInfo.cpp | 644 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
672 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
709 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
745 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
781 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
782 return X86::RDI; in getX86SubSuperRegisterOrZero()
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| D | X86CallingConv.td | 212 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
278 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
340 RDI, RSI, RDX, RCX, R8, R9,
429 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
718 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
807 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
817 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
826 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
842 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
846 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
[all …]
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| D | X86InstrSystem.td | 533 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
538 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
546 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
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| D | X86RegisterInfo.td | 134 def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
375 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
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| /external/libunwind/src/x86_64/ |
| D | init.h | 54 c->dwarf.loc[RDI] = REG_INIT_LOC(c, rdi, RDI); in common_init()
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| D | unwind_i.h | 44 #define RDI 5 macro
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| D | Gregs.c | 112 case UNW_X86_64_RDI: loc = c->dwarf.loc[RDI]; break; in tdep_access_reg()
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| /external/strace/linux/x86_64/ |
| D | userent.h | 15 XLAT(8*RDI),
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 47 #define RDI 112 macro
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| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-amd64-darwin.c | 101 SC2(__rdi,RDI); in synthesize_ucontext()
129 SC2(RDI,__rdi); in restore_from_ucontext()
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| /external/lzma/Asm/x86/ |
| D | 7zAsm.asm | 73 r7 equ RDI
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| /external/llvm/test/DebugInfo/X86/ |
| D | debug-loc-asan.ll | 13 ; in RDI, after which it is spilled to the stack. We record the
15 ; CHECK: #DEBUG_VALUE: bar:y <- [%RDI+0]
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 163 X86::RCX, X86::RDX, X86::RDI, in ChooseFrameReg()
423 X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */, in InstrumentMOV()
877 if (RegCtx.AddressReg(MVT::i64) != X86::RDI) { in EmitCallAsanReport()
878 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg( in EmitCallAsanReport()
1021 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */, in InstrumentMOVSImpl()
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| D | X86Operand.h | 312 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI || in isDstIdx()
399 case X86::RDI: return X86::EDI; in getGR32FromGR64()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 178 ENTRY(RDI) \
196 ENTRY(RDI) \
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| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 129 CHECK_REG(RDI); in TEST()
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| /external/llvm/test/MC/X86/ |
| D | intel-syntax.s | 59 mov EAX, DWORD PTR FS:[RDI]
61 lea R8D, DWORD PTR [4*RDI]
|