| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 852 SETUEQ, // 1 0 0 1 True if unordered or equal enumerator
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 39 case ISD::SETOEQ: case ISD::SETUEQ:
|
| D | R600ISelLowering.cpp | 449 case ISD::SETUEQ: in LowerSELECT_CC()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 174 case FCmpInst::FCMP_UEQ: return ISD::SETUEQ; in getFCmpCondCode()
187 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 107 def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
136 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
|
| D | R600ISelLowering.cpp | 53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
|
| D | AMDGPUISelLowering.cpp | 1105 case ISD::SETUEQ: in CombineFMinMaxLegacy()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 339 case ISD::SETUEQ: return "setueq"; in getOperationName()
|
| D | TargetLowering.cpp | 179 case ISD::SETUEQ: in softenSetCCOperands()
1833 if (Cond == ISD::SETUEQ && in SimplifySetCC()
1846 if (Cond == ISD::SETUEQ && in SimplifySetCC()
|
| D | SelectionDAG.cpp | 335 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
1941 case ISD::SETUEQ: in FoldSetCC()
2001 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
|
| D | LegalizeDAG.cpp | 1860 case ISD::SETUEQ: in LegalizeSetCCCondCode()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 131 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2094 case ISD::SETUEQ: in getPredicateForSetCC()
2141 case ISD::SETUEQ: in getCRIdxForSetCC()
2218 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
2226 case ISD::SETUEQ: in getVCmpInst()
|
| D | PPCInstrQPX.td | 1004 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUEQ),
1051 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUEQ),
|
| D | PPCISelLowering.cpp | 351 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
352 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
549 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
594 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
|
| D | PPCInstrInfo.td | 2923 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 582 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
965 (setcc node:$lhs, node:$rhs, SETUEQ)>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 966 (setcc node:$lhs, node:$rhs, SETUEQ)>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 175 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
176 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
|
| D | MipsSEISelLowering.cpp | 1822 Op->getOperand(2), ISD::SETUEQ); in lowerINTRINSIC_WO_CHAIN()
|
| D | MipsISelLowering.cpp | 529 case ISD::SETUEQ: return Mips::FCOND_UEQ; in condCodeToFCC()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1420 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1113 case ISD::SETUEQ: in changeFPCCToAArch64CC()
1158 case ISD::SETUEQ: in changeVectorFPCCToAArch64CC()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1345 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; in FPCCToARMCC()
4646 case ISD::SETUEQ: Invert = true; // Fallthrough in LowerVSETCC()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2269 case ISD::SETUEQ: in lowerVectorSETCC()
|