Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 432 SIGN_EXTEND_VECTOR_INREG, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 328 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
704 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 245 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
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| D | DAGCombiner.cpp | 1405 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); in visit()
5733 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
5769 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
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| D | SelectionDAG.cpp | 1067 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 815 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 320 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4405 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
4601 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
15410 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) && in LowerExtendedLoad()
20085 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
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