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Searched refs:SRC0 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/mesa/x86/
Dx86_xform3.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
208 FLD_S( SRC0 ) /* F4 */
288 FLD_S( SRC0 ) /* F4 */
290 FLD_S( SRC0 ) /* F5 F4 */
292 FLD_S( SRC0 ) /* F6 F5 F4 */
383 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_xform2.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
194 FLD_S( SRC0 ) /* F4 */
257 FLD_S( SRC0 ) /* F4 */
259 FLD_S( SRC0 ) /* F5 F4 */
261 FLD_S( SRC0 ) /* F6 F5 F4 */
342 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_xform4.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
215 FLD_S( SRC0 ) /* F4 */
298 FLD_S( SRC0 ) /* F4 */
300 FLD_S( SRC0 ) /* F5 F4 */
302 FLD_S( SRC0 ) /* F6 F5 F4 */
401 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_cliptest.S36 #define SRC0 REGOFF(0, ESI) macro
189 MOV_L( SRC0, EBX )
227 FLD_S( SRC0 ) /* F0 F3 */
355 MOV_L( SRC0, EBX )
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td373 bits<9> SRC0;
375 let Inst{8-0} = SRC0;
388 bits<9> SRC0;
391 let Inst{8-0} = SRC0;
405 bits<9> SRC0;
418 let Inst{40-32} = SRC0;
431 bits<9> SRC0;
434 let Inst{8-0} = SRC0;
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll49 ; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
52 ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
100 ; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
105 ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
Dllvm.AMDGPU.umad24.ll22 ; SI-DAG: buffer_load_dword [[SRC0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
24 ; SI: v_mad_u32_u24 [[RESULT:v[0-9]+]], 4, [[SRC0]], [[SRC2]]
Dmul.ll111 ; SI: s_load_dword [[SRC0:s[0-9]+]],
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/webp/src/dsp/
Drescaler_neon.c31 #define STORE_32x8(SRC0, SRC1, DST) do { \ argument
32 vst1q_u32((DST) + 0, SRC0); \