| /external/bison/lib/ |
| D | bitset.h | 244 #define bitset_and_or(DST, SRC1, SRC2, SRC3) \ argument
245 BITSET_AND_OR_ (DST, SRC1, SRC2, SRC3)
249 #define bitset_and_or_cmp(DST, SRC1, SRC2, SRC3) \ argument
250 BITSET_AND_OR_CMP_ (DST, SRC1, SRC2, SRC3)
253 #define bitset_andn_or(DST, SRC1, SRC2, SRC3) \ argument
254 BITSET_ANDN_OR_ (DST, SRC1, SRC2, SRC3)
258 #define bitset_andn_or_cmp(DST, SRC1, SRC2, SRC3) \ argument
259 BITSET_ANDN_OR_CMP_ (DST, SRC1, SRC2, SRC3)
262 #define bitset_or_and(DST, SRC1, SRC2, SRC3)\ argument
263 BITSET_OR_AND_ (DST, SRC1, SRC2, SRC3)
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| D | bbitset.h | 168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ argument
170 || !BITSET_COMPATIBLE_ (DST, SRC3)) abort ();
249 #define BITSET_AND_OR_(DST, SRC1, SRC2, SRC3) \ argument
250 (SRC1)->b.vtable->and_or (DST, SRC1, SRC2, SRC3)
251 #define BITSET_AND_OR_CMP_(DST, SRC1, SRC2, SRC3) \ argument
252 (SRC1)->b.vtable->and_or_cmp (DST, SRC1, SRC2, SRC3)
256 #define BITSET_ANDN_OR_(DST, SRC1, SRC2, SRC3) \ argument
257 (SRC1)->b.vtable->andn_or (DST, SRC1, SRC2, SRC3)
258 #define BITSET_ANDN_OR_CMP_(DST, SRC1, SRC2, SRC3) \ argument
259 (SRC1)->b.vtable->andn_or_cmp (DST, SRC1, SRC2, SRC3)
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| /external/mesa3d/src/mesa/x86/ |
| D | x86_xform4.S | 44 #define SRC3 REGOFF(12, ESI) macro
141 FLD_S( SRC3 ) /* F0 F7 F6 F5 F4 */
143 FLD_S( SRC3 ) /* F1 F0 F7 F6 F5 F4 */
145 FLD_S( SRC3 ) /* F2 F1 F0 F7 F6 F5 F4 */
147 FLD_S( SRC3 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
232 FLD_S( SRC3 ) /* F2 F6 F5 F4 */
329 FLD_S( SRC3 ) /* F0 F6 F5 F4 */
331 FLD_S( SRC3 ) /* F1 F0 F6 F5 F4 */
333 FLD_S( SRC3 ) /* F2 F1 F0 F6 F5 F4 */
341 MOV_L( SRC3, EBX )
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| D | x86_cliptest.S | 39 #define SRC3 REGOFF(12, ESI) macro
166 FDIV_S( SRC3 ) /* GH: don't care about div-by-zero */
168 MOV_L( SRC3, EBP )
334 MOV_L( SRC3, EBP )
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| D | x86_xform2.S | 44 #define SRC3 REGOFF(12, ESI) macro
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| D | x86_xform3.S | 44 #define SRC3 REGOFF(12, ESI) macro
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sminmax.ll | 103 ; GCN: v_sub_i32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]]
108 ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]]
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