| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1301 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1303 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1304 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1314 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1315 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1322 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1323 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1336 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1343 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1344 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
[all …]
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 241 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
242 if (SrcOp > DestOp) { in ParseConstraint()
243 std::swap(SrcOp, DestOp); in ParseConstraint()
247 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
|
| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1024 const MachineOperand &SrcOp, in getShuffleComment() argument
1038 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem"; in getShuffleComment()
1283 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1290 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask)); in EmitInstruction()
1303 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1310 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask)); in EmitInstruction()
|
| D | X86ISelLowering.cpp | 5294 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, in getVShift() argument
5300 SrcOp = DAG.getBitcast(ShVT, SrcOp); in getVShift()
5304 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
5308 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) { in LowerAsSplatVectorLoad() argument
5313 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { in LowerAsSplatVectorLoad()
15973 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode() argument
15979 return SrcOp; in getTargetVShiftByConstNode()
15994 if (VT == SrcOp.getSimpleValueType() && in getTargetVShiftByConstNode()
15995 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) { in getTargetVShiftByConstNode()
15997 unsigned NumElts = SrcOp->getNumOperands(); in getTargetVShiftByConstNode()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 158 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
683 MachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp, in genTfrFor() argument
685 MachineInstr *MI = SrcOp.getParent(); in genTfrFor()
696 unsigned Opc = getCondTfrOpcode(SrcOp, Cond); in genTfrFor()
700 .addOperand(SrcOp); in genTfrFor()
|
| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2426 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
2427 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
2436 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
2443 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2456 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
2472 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2515 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2530 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2562 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
2571 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 806 const MachineOperand &SrcOp = MI->getOperand(1); in expandPostRAPseudo() local
808 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
809 if (SrcOp.isImm()) { in expandPostRAPseudo()
810 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
818 assert(SrcOp.isReg()); in expandPostRAPseudo()
820 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
823 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
|
| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 2527 Value *SrcOp = Instr->getOperand(op); in scalarizeInstruction() local
2530 if (SrcOp == OldInduction) { in scalarizeInstruction()
2531 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
2536 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
2547 Scalars.append(UF, SrcOp); in scalarizeInstruction()
5720 Value *SrcOp = Instr->getOperand(op); in scalarizeInstruction() local
5723 if (SrcOp == OldInduction) { in scalarizeInstruction()
5724 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
5729 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
5740 Scalars.append(UF, SrcOp); in scalarizeInstruction()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
1921 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, in EmitStackConvert() argument
1927 SrcOp.getValueType().getTypeForEVT(*DAG.getContext())); in EmitStackConvert()
1935 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); in EmitStackConvert()
1946 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
1950 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
|