| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef() local
198 unsigned SubReg = *SubRegs; in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef() local
221 SubRegs.isValid(); ++SubRegs) in FindLastPartialDef()
222 PartDefRegs.insert(*SubRegs); in FindLastPartialDef()
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse()
274 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse() local
275 SubRegs.isValid(); ++SubRegs) in HandlePhysRegUse()
276 PhysRegUse[*SubRegs] = MI; in HandlePhysRegUse()
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| D | MachineVerifier.cpp | 94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs() local
95 RV.push_back(*SubRegs); in addRegWithSubRegs()
475 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in visitMachineFunctionBefore() local
478 regsReserved.set(*SubRegs); in visitMachineFunctionBefore()
699 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true); in visitMachineBasicBlockBefore() local
700 SubRegs.isValid(); ++SubRegs) in visitMachineBasicBlockBefore()
701 regsLive.insert(*SubRegs); in visitMachineBasicBlockBefore()
709 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true); in visitMachineBasicBlockBefore() local
710 SubRegs.isValid(); ++SubRegs) in visitMachineBasicBlockBefore()
711 regsLive.insert(*SubRegs); in visitMachineBasicBlockBefore()
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| D | CriticalAntiDepBreaker.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
218 SubRegs.isValid(); ++SubRegs) { in PrescanInstruction()
219 KeepRegs.set(*SubRegs); in PrescanInstruction()
229 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
230 SubRegs.isValid(); ++SubRegs) in PrescanInstruction()
231 KeepRegs.set(*SubRegs); in PrescanInstruction()
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| D | ScheduleDAGInstrs.cpp | 1168 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true); in startBlockForKills() local
1169 SubRegs.isValid(); ++SubRegs) in startBlockForKills()
1170 LiveRegs.set(*SubRegs); in startBlockForKills()
1237 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { in toggleKillFlag() local
1238 if (LiveRegs.test(*SubRegs)) { in toggleKillFlag()
1239 MIB.addReg(*SubRegs, RegState::ImplicitDefine); in toggleKillFlag()
1283 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in fixupKills() local
1284 SubRegs.isValid(); ++SubRegs) in fixupKills()
1285 LiveRegs.reset(*SubRegs); in fixupKills()
1302 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in fixupKills() local
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| D | MachineInstrBundle.cpp | 186 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in finalizeBundle() local
187 unsigned SubReg = *SubRegs; in finalizeBundle()
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| D | RegisterScavenging.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward() local
218 if (isRegUsed(*SubRegs)) { in forward()
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| D | AggressiveAntiDepBreaker.cpp | 244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs() local
245 SubRegs.isValid(); ++SubRegs) in GetPassthruRegs()
246 PassthruRegs.insert(*SubRegs); in GetPassthruRegs()
318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse() local
319 unsigned SubregReg = *SubRegs; in HandleLastUse()
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| D | BranchFolding.cpp | 157 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in OptimizeImpDefsBlock() local
158 SubRegs.isValid(); ++SubRegs) in OptimizeImpDefsBlock()
159 ImpDefRegs.insert(*SubRegs); in OptimizeImpDefsBlock()
1718 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findHoistingInsertPosAndDeps() local
1719 Uses.erase(*SubRegs); // Use sub-registers to be conservative in findHoistingInsertPosAndDeps()
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| D | IfConversion.cpp | 1456 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamond() local
1457 SubRegs.isValid(); ++SubRegs) in IfConvertDiamond()
1458 ExtUses.insert(*SubRegs); in IfConvertDiamond()
1465 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamond() local
1466 SubRegs.isValid(); ++SubRegs) in IfConvertDiamond()
1467 RedefsByFalse.insert(*SubRegs); in IfConvertDiamond()
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| /external/llvm/include/llvm/CodeGen/ |
| D | LivePhysRegs.h | 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg()
78 SubRegs.isValid(); ++SubRegs) in addReg()
79 LiveRegs.insert(*SubRegs); in addReg()
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in removeReg()
88 SubRegs.isValid(); ++SubRegs) in removeReg()
89 LiveRegs.erase(*SubRegs); in removeReg()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterInfo.cpp | 46 static const unsigned SubRegs[] = { in getSubRegFromChannel() local
53 assert(Channel < array_lengthof(SubRegs)); in getSubRegFromChannel()
54 return SubRegs[Channel]; in getSubRegFromChannel()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); in inheritRegUnits()
218 return SubRegs; in computeSubRegs()
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second) in computeSubRegs()
247 if (!SubRegs.insert(*SI).second) in computeSubRegs()
260 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
298 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
303 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second; in computeSubRegs()
307 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end(); in computeSubRegs()
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| D | CodeGenRegisters.h | 159 return SubRegs; in getSubRegs()
252 SubRegMap SubRegs; member
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 38 let SubRegs = [SubReg];
55 let SubRegs = [SubReg];
70 let SubRegs = [SubReg];
78 let SubRegs = [SubReg];
87 let SubRegs = [SubReg];
94 let SubRegs = subregs;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 201 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { in getMax32BitSubRegister() local
203 if (*SubRegs > RegNo) in getMax32BitSubRegister()
204 RegNo = *SubRegs; in getMax32BitSubRegister()
206 if (!RegNo || *SubRegs < RegNo) in getMax32BitSubRegister()
207 RegNo = *SubRegs; in getMax32BitSubRegister()
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| D | HexagonCopyToCombine.cpp | 389 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in findPotentialNewifiableTFRs() local
390 LastDef[*SubRegs] = MI; in findPotentialNewifiableTFRs()
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| D | HexagonRegisterInfo.td | 48 let SubRegs = subregs;
74 let SubRegs = subregs;
146 let SubRegs = [USR_OVF];
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| D | HexagonInstrInfo.cpp | 1736 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
1737 if (RegB == *SubRegs) in isDependent()
1741 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
1742 if (RegA == *SubRegs) in isDependent()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 107 uint32_t SubRegs; // Sub-register set, described above member
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 37 let SubRegs = subregs;
46 let SubRegs = subregs;
53 let SubRegs = subregs;
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 48 // in the SubRegs field of a Register definition. For example:
90 // SubRegs - A list of registers that are parts of this register. Note these
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
98 // SubRegs.
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
137 let SubRegs = subregs;
279 // SubRegs - N lists of registers to be zipped up. Super-registers are
280 // synthesized from the first element of each SubRegs list, the second
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 741 unsigned SubRegs = 0; in copyPhysReg() local
748 SubRegs = 2; in copyPhysReg()
752 SubRegs = 4; in copyPhysReg()
757 SubRegs = 2; in copyPhysReg()
761 SubRegs = 3; in copyPhysReg()
765 SubRegs = 4; in copyPhysReg()
769 SubRegs = 2; in copyPhysReg()
773 SubRegs = 2; in copyPhysReg()
778 SubRegs = 3; in copyPhysReg()
783 SubRegs = 4; in copyPhysReg()
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 25 let SubRegs = subregs;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 148 const unsigned SubRegs[]);
974 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
977 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
983 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
986 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
991 const unsigned SubRegs[]) { in createTuple() argument
1010 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32)); in createTuple()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 359 list<Register> SubRegs = [];
401 const unsigned *SubRegs; // Sub-register set
417 specify subregisters in the ``SubRegs`` list, as shown here:
422 let SubRegs = subregs;
429 override values that are initially defined in a superclass (such as ``SubRegs``
451 let SubRegs = subregs;
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