Searched refs:UADDO (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 SADDO, UADDO, enumerator
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| D | SelectionDAG.h | 1097 case ISD::UADDO:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 129 case ISD::UADDO: in PromoteIntegerResult()
739 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_UADDSUBO()
1389 case ISD::UADDO: in ExpandIntegerResult()
1713 ISD::UADDO : ISD::USUBO, in ExpandIntRes_ADDSUB()
1721 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2436 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? in ExpandIntRes_UADDSUBO()
2444 N->getOpcode () == ISD::UADDO ? in ExpandIntRes_UADDSUBO()
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| D | SelectionDAGDumper.cpp | 228 case ISD::UADDO: return "uaddo"; in getOperationName()
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| D | LegalizeDAG.cpp | 3576 case ISD::UADDO: in ExpandNode()
3580 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? in ExpandNode()
3588 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
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| D | SelectionDAG.cpp | 2151 case ISD::UADDO: in computeKnownBits()
2612 case ISD::UADDO: in ComputeNumSignBits()
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| D | SelectionDAGBuilder.cpp | 5081 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; in visitIntrinsicCall()
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| D | DAGCombiner.cpp | 2678 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(), in visitUMULO()
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| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 174 ; UADDO
199 ; UADDO reg, 1 | NOT INC
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 97 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
597 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 254 setOperationAction(ISD::UADDO, MVT::i32, Custom); in AArch64TargetLowering()
255 setOperationAction(ISD::UADDO, MVT::i64, Custom); in AArch64TargetLowering()
1560 case ISD::UADDO: in getAArch64XALUOOp()
2273 case ISD::UADDO: in LowerOperation()
3603 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
4052 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 801 setOperationAction(ISD::UADDO, VT, Expand); in initActions()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1661 setOperationAction(ISD::UADDO, VT, Expand); in HexagonTargetLowering()
1750 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO, in HexagonTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 718 setOperationAction(ISD::UADDO, MVT::i32, Custom); in ARMTargetLowering()
3405 case ISD::UADDO: in getARMXALUOOp()
3458 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
6884 case ISD::UADDO: in LowerOperation()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1758 setOperationAction(ISD::UADDO, VT, Custom); in X86TargetLowering()
14991 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
15000 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; in LowerSELECT()
15471 Cond.getOperand(0).getOpcode() == ISD::UADDO || in LowerBRCOND()
15526 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND()
15539 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; in LowerBRCOND()
19075 case ISD::UADDO: in LowerXALUO()
20129 case ISD::UADDO: in LowerOperation()
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