| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 403 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
407 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
411 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
415 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
420 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
424 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
428 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
432 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
228 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
229 { ISD::UDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
274 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence in getArithmeticInstrCost()
276 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
358 { ISD::UDIV, MVT::v16i8, 16*20 }, in getArithmeticInstrCost()
359 { ISD::UDIV, MVT::v8i16, 8*20 }, in getArithmeticInstrCost()
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 207 setOperationAction(ISD::UDIV, MVT::v2i8, Expand); in InitAMDILLowering()
208 setOperationAction(ISD::UDIV, MVT::v4i8, Expand); in InitAMDILLowering()
209 setOperationAction(ISD::UDIV, MVT::v2i16, Expand); in InitAMDILLowering()
210 setOperationAction(ISD::UDIV, MVT::v4i16, Expand); in InitAMDILLowering()
623 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1); in LowerSDIV32()
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| D | AMDGPUISelLowering.cpp | 39 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
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| /external/compiler-rt/lib/builtins/arm/ |
| D | umodsi3.S | 78 # error THUMB mode requires CLZ or UDIV
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| D | udivsi3.S | 82 # error THUMB mode requires CLZ or UDIV
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| D | udivmodsi4.S | 82 # error THUMB mode requires CLZ or UDIV
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 155 OP12(UDIV)
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1665 case ISD::UDIV: in selectDivRem()
1667 DivOpc = Mips::UDIV; in selectDivRem()
1782 if (!selectBinaryOp(I, ISD::UDIV)) in fastSelectInstruction()
1783 return selectDivRem(I, ISD::UDIV); in fastSelectInstruction()
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| D | MipsSEISelLowering.cpp | 169 setOperationAction(ISD::UDIV, MVT::i32, Legal); in MipsSETargetLowering()
216 setOperationAction(ISD::UDIV, MVT::i64, Legal); in MipsSETargetLowering()
272 setOperationAction(ISD::UDIV, Ty, Legal); in addMSAIntType()
1790 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 340 case ISD::UDIV: { in Select()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 181 case ISD::UDIV: return "udiv"; in getOperationName()
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| D | SelectionDAGBuilder.h | 784 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } in visitUDiv()
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| D | FastISel.cpp | 1557 return selectBinaryOp(I, ISD::UDIV); in selectOperator()
1725 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { in fastEmit_ri_()
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| D | LegalizeVectorOps.cpp | 265 case ISD::UDIV: in LegalizeOp()
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| D | LegalizeIntegerTypes.cpp | 124 case ISD::UDIV: in PromoteIntegerResult()
1327 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; in ExpandIntegerResult()
2469 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero); in ExpandIntRes_XMULO()
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| D | LegalizeVectorTypes.cpp | 127 case ISD::UDIV: in ScalarizeVectorResult()
675 case ISD::UDIV: in SplitVectorResult()
2052 case ISD::UDIV: in WidenVectorResult()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 122 #define UDIV 0x9ac00800 macro
1267 …FAIL_IF(push_inst(compiler, ((op == SLJIT_UDIVMOD ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(S… in sljit_emit_op0()
1272 …return push_inst(compiler, ((op == SLJIT_UDIVI ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJI… in sljit_emit_op0()
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| D | sljitNativeSPARC_common.c | 173 #define UDIV (OPC1(0x2) | OPC3(0x0e)) macro
794 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_UDIVI ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0)… in sljit_emit_op0()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 150 setOperationAction(ISD::UDIV, MVT::i8, Expand); in MSP430TargetLowering()
156 setOperationAction(ISD::UDIV, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 887 case ISD::UDIV: in canOpTrap()
1560 case UDiv: return ISD::UDIV; in InstructionOpcodeToISD()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 938 UDIV = UDIV_w, enumerator
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| D | disasm-arm64.cc | 599 FORMAT(UDIV, "udiv"); in VisitDataProcessing2Source()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 272 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
312 setOperationAction(ISD::UDIV, VT, Expand); in AMDGPUTargetLowering()
1681 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
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