| /external/strace/xlat/ |
| D | atomic_ops.in | 8 { OR1K_ATOMIC_UMAX, "UMAX" },
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 262 X86_INTRINSIC_DATA(avx2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0),
263 X86_INTRINSIC_DATA(avx2_pmaxu_d, INTR_TYPE_2OP, ISD::UMAX, 0),
264 X86_INTRINSIC_DATA(avx2_pmaxu_w, INTR_TYPE_2OP, ISD::UMAX, 0),
966 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
967 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
968 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
969 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
970 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
971 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
972 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
[all …]
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| D | X86ISelLowering.cpp | 847 setOperationAction(ISD::UMAX, MVT::v16i8, Legal); in X86TargetLowering()
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal); in X86TargetLowering()
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal); in X86TargetLowering()
1196 setOperationAction(ISD::UMAX, MVT::v32i8, Legal); in X86TargetLowering()
1197 setOperationAction(ISD::UMAX, MVT::v16i16, Legal); in X86TargetLowering()
1198 setOperationAction(ISD::UMAX, MVT::v8i32, Legal); in X86TargetLowering()
1243 setOperationAction(ISD::UMAX, MVT::v32i8, Custom); in X86TargetLowering()
1244 setOperationAction(ISD::UMAX, MVT::v16i16, Custom); in X86TargetLowering()
1245 setOperationAction(ISD::UMAX, MVT::v8i32, Custom); in X86TargetLowering()
1494 setOperationAction(ISD::UMAX, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.td | 46 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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| D | AMDGPUISelLowering.h | 119 UMAX, enumerator
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| D | AMDGPUISelLowering.cpp | 130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
347 NODE_NAME_CASE(UMAX) in getTargetNodeName()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 322 SMIN, SMAX, UMIN, UMAX, enumerator
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| D | SelectionDAG.h | 1085 case ISD::UMAX:
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 157 OP12(UMAX)
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| /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/ |
| D | sm4_to_tgsi.cpp | 513 OP2(UMAX); in translate_insns()
560 OP2_(UMAX, MAX); in translate_insns()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.td | 88 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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| D | SIISelLowering.cpp | 261 setTargetDAGCombine(ISD::UMAX); in SITargetLowering()
1904 case ISD::UMAX: in minMaxOpcToMin3Max3Opc()
1998 case ISD::UMAX: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 283 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
979 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 209 case ISD::UMAX: return "umax"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 333 case ISD::UMAX: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 117 case ISD::UMAX: in ScalarizeVectorResult()
690 case ISD::UMAX: in SplitVectorResult()
2041 case ISD::UMAX: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2484 case ISD::UMAX: { in computeKnownBits()
2605 case ISD::UMAX: in ComputeNumSignBits()
3204 case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true); in FoldValue()
3490 case ISD::UMAX: in getNode()
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| D | LegalizeDAG.cpp | 3351 case ISD::UMAX: { in ExpandNode()
3358 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
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| /external/llvm/test/Transforms/InstCombine/ |
| D | select.ll | 494 ; UMAX(UMAX(x, y), x) -> UMAX(x, y)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 697 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2224 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
8869 case ISD::UMAX: in tryMatchAcrossLaneShuffleForReduction()
8946 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN && in performAcrossLaneMinMaxReductionCombine()
8979 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) || in performAcrossLaneMinMaxReductionCombine()
9862 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV); in ReplaceNodeResults()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 796 setOperationAction(ISD::UMAX, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 397 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 536 NV50_IR_OPCODE_CASE(UMAX, MAX); in translateOpcode()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 661 case3(MAX, IMAX, UMAX); in get_opcode()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 4178 ### UMAX ### subsection
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