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Searched refs:UMIN (Results 1 – 25 of 36) sorted by relevance

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/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1.s183UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
194UMIN v1.8h, v1.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
205UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
208UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
237UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
243UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
313UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
319UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
348UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class1_chroma.s219UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
240UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
253UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
256UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
297UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
303UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
394UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
406UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
447UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class0.s221UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
232UMIN v21.8h, v21.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
241UMIN v0.8h, v0.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
248UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
322UMIN v28.8h, v28.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class2.s336UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
345UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
433UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
438UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
444UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
457UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
514UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
520UMIN v5.8h, v5.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
650UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
656UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class3.s348UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
354UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
452UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
462UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
469UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
478UMIN v22.8h, v22.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
544UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
548UMIN v22.8h, v22.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
688UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
694UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class0_chroma.s259UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
269UMIN v19.8h, v19.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
292UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
304UMIN v30.8h, v30.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
436UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
465UMIN v24.8h, v24.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
Dihevc_sao_edge_offset_class3_chroma.s459UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
467UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
609UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
624UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
631UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
638UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
720UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
724UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
909UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
915UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class2_chroma.s476UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
481UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
609UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
631UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
644UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
652UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
730UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
734UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
897UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
902UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
/external/strace/xlat/
Datomic_ops.in9 { OR1K_ATOMIC_UMIN, "UMIN" },
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h268 X86_INTRINSIC_DATA(avx2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0),
269 X86_INTRINSIC_DATA(avx2_pminu_d, INTR_TYPE_2OP, ISD::UMIN, 0),
270 X86_INTRINSIC_DATA(avx2_pminu_w, INTR_TYPE_2OP, ISD::UMIN, 0),
990 X86_INTRINSIC_DATA(avx512_mask_pminu_b_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
991 X86_INTRINSIC_DATA(avx512_mask_pminu_b_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
992 X86_INTRINSIC_DATA(avx512_mask_pminu_b_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
993 X86_INTRINSIC_DATA(avx512_mask_pminu_d_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
994 X86_INTRINSIC_DATA(avx512_mask_pminu_d_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
995 X86_INTRINSIC_DATA(avx512_mask_pminu_d_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
996 X86_INTRINSIC_DATA(avx512_mask_pminu_q_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
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DX86ISelLowering.cpp849 setOperationAction(ISD::UMIN, MVT::v16i8, Legal); in X86TargetLowering()
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal); in X86TargetLowering()
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal); in X86TargetLowering()
1202 setOperationAction(ISD::UMIN, MVT::v32i8, Legal); in X86TargetLowering()
1203 setOperationAction(ISD::UMIN, MVT::v16i16, Legal); in X86TargetLowering()
1204 setOperationAction(ISD::UMIN, MVT::v8i32, Legal); in X86TargetLowering()
1249 setOperationAction(ISD::UMIN, MVT::v32i8, Custom); in X86TargetLowering()
1250 setOperationAction(ISD::UMIN, MVT::v16i16, Custom); in X86TargetLowering()
1251 setOperationAction(ISD::UMIN, MVT::v8i32, Custom); in X86TargetLowering()
1498 setOperationAction(ISD::UMIN, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstrInfo.td61 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
DAMDGPUISelLowering.h122 UMIN, enumerator
DAMDGPUISelLowering.cpp139 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
350 NODE_NAME_CASE(UMIN) in getTargetNodeName()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h322 SMIN, SMAX, UMIN, UMAX, enumerator
DSelectionDAG.h1084 case ISD::UMIN:
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h158 OP12(UMIN)
/external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/
Dsm4_to_tgsi.cpp512 OP2(UMIN); in translate_insns()
559 OP2_(UMIN, MIN); in translate_insns()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp208 case ISD::UMIN: return "umin"; in getOperationName()
DLegalizeVectorOps.cpp332 case ISD::UMIN: in LegalizeOp()
DLegalizeVectorTypes.cpp116 case ISD::UMIN: in ScalarizeVectorResult()
689 case ISD::UMIN: in SplitVectorResult()
2040 case ISD::UMIN: in WidenVectorResult()
DSelectionDAG.cpp2483 case ISD::UMIN: in computeKnownBits()
2604 case ISD::UMIN: in ComputeNumSignBits()
3203 case ISD::UMIN: return std::make_pair(C1.ule(C2) ? C1 : C2, true); in FoldValue()
3489 case ISD::UMIN: in getNode()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp260 setTargetDAGCombine(ISD::UMIN); in SITargetLowering()
1910 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
1999 case ISD::UMIN: { in PerformDAGCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp697 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2230 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
8875 case ISD::UMIN: in tryMatchAcrossLaneShuffleForReduction()
8947 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
8981 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) || in performAcrossLaneMinMaxReductionCombine()
9856 ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV); in ReplaceNodeResults()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp795 setOperationAction(ISD::UMIN, VT, Expand); in initActions()

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