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Searched refs:V2S (Results 1 – 5 of 5) sorted by relevance

/external/vixl/test/
Dtest-disasm-a64.cc2814 V(V2S(), "2s") \
2820 V(V2S(), "2s", V4H(), "4h") \
2821 V(V1D(), "1d", V2S(), "2s") \
2829 V(V2D(), "2d", V2S(), "2s")
2841 V(V2S(), "2s") \
2847 V(V2S(), "2s") \
2905 COMPARE(Ld1(v16.V2S(), v17.V2S(), v18.V2S(), MemOperand(x19, 24, PostIndex)), in TEST()
2909 COMPARE(Ld1(v19.V2S(), v20.V2S(), v21.V2S(), v22.V2S(), in TEST()
2920 COMPARE(Ld3(v16.V2S(), v17.V2S(), v18.V2S(), MemOperand(x19, 24, PostIndex)), in TEST()
2924 COMPARE(Ld4(v19.V2S(), v20.V2S(), v21.V2S(), v22.V2S(), in TEST()
[all …]
Dtest-assembler-a64.cc2925 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), MemOperand(x17)); in TEST()
2927 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST()
2978 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), in TEST()
2980 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), in TEST()
3191 __ Ld2(v31.V2S(), v0.V2S(), MemOperand(x17)); in TEST()
3227 __ Ld2(v16.V2S(), v17.V2S(), MemOperand(x20, 16, PostIndex)); in TEST()
3228 __ Ld2(v31.V2S(), v0.V2S(), MemOperand(x21, 16, PostIndex)); in TEST()
3538 __ Ld2r(v8.V2S(), v9.V2S(), MemOperand(x17)); in TEST()
3582 __ Ld2r(v8.V2S(), v9.V2S(), MemOperand(x17, x18, PostIndex)); in TEST()
3626 __ Ld3(v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST()
[all …]
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.cc971 Movi32bitHelper(vd.Is64Bits() ? vd.V2S() : vd.V4S(), imm & 0xffffffff); in Movi64bitHelper()
Dassembler-a64.h298 VRegister V2S() const { return VRegister(code_, kDRegSize, 2); } in V2S() function
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp7969 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(), in lowerVectorShuffleAsElementInsertion() local
7971 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) { in lowerVectorShuffleAsElementInsertion()
7973 V2S = DAG.getBitcast(EltVT, V2S); in lowerVectorShuffleAsElementInsertion()
7982 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S); in lowerVectorShuffleAsElementInsertion()
7984 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerVectorShuffleAsElementInsertion()