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/external/llvm/test/CodeGen/AMDGPU/
Dglobal_atomics.ll2 …=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=VI --check-prefix=FUNC …
27 ; VI: s_movk_i32 flat_scratch_lo, 0x0
28 ; VI: s_movk_i32 flat_scratch_hi, 0x0
29 ; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
41 ; VI: s_movk_i32 flat_scratch_lo, 0x0
42 ; VI: s_movk_i32 flat_scratch_hi, 0x0
43 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
74 ; VI: s_movk_i32 flat_scratch_lo, 0x0
75 ; VI: s_movk_i32 flat_scratch_hi, 0x0
76 ; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
[all …]
Dllvm.amdgcn.s.dcache.wb.ll1 ; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
5 ; VI-LABEL: {{^}}test_s_dcache_wb:
6 ; VI-NEXT: ; BB#0:
7 ; VI-NEXT: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
8 ; VI-NEXT: s_endpgm
14 ; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait:
15 ; VI-NEXT: ; BB#0:
16 ; VI-NEXT: s_dcache_wb
17 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding
Dllvm.amdgcn.s.dcache.wb.vol.ll1 ; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
5 ; VI-LABEL: {{^}}test_s_dcache_wb_vol:
6 ; VI-NEXT: ; BB#0:
7 ; VI-NEXT: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
8 ; VI-NEXT: s_endpgm
14 ; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait:
15 ; VI-NEXT: ; BB#0:
16 ; VI-NEXT: s_dcache_wb_vol
17 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding
Dllvm.AMDGPU.rsq.clamped.f64.ll2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
9 ; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3]
11 ; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
12 ; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
13 ; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
14 ; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
15 ; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
16 ; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
17 ; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
Dsra.ll3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s
13 ;VI-LABEL: {{^}}ashr_v2i32:
14 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
15 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
38 ;VI-LABEL: {{^}}ashr_v4i32:
39 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
40 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
41 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
59 ;VI-LABEL: {{^}}ashr_i64:
[all …]
Dllvm.r600.read.local.size.ll2 … -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -chec…
11 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
13 ; VI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x4
29 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
44 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
57 ; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
58 ; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
75 ; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
76 ; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
96 ; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
[all …]
Dshl.ll3 …s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s
16 ;VI: {{^}}shl_v2i32:
17 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
18 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
41 ;VI: {{^}}shl_v4i32:
42 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
43 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
71 ;VI: {{^}}shl_i64:
[all …]
Dllvm.AMDGPU.rsq.clamped.ll2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
11 ; VI: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}}
12 ; VI: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
14 ; VI: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff
15 ; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]]
Dschedule-kernel-arg-loads.ll2 …ga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI --check-prefix=GCN %s
9 ; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24
10 ; VI-NEXT: s_nop 0
11 ; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
12 ; VI-NEXT: s_nop 0
13 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
14 ; VI-NEXT: s_nop 0
15 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
Dsrl.ll2 ; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
9 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
25 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
46 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
47 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
[all …]
Datomic_cmp_swap_local.ll3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
9 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
10 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
28 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
29 ; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
61 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
62 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28
78 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
79 ; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
Dsmrd.ll3 …u=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN -…
8 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
20 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
34 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
49 ; TODO: Add VI checks
59 ; SMRD load with the largest possible immediate offset on VI
64 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
73 ; SMRD load with an offset greater than the largest possible immediate on VI
90 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
104 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
[all …]
Dkernel-args.ll2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --…
9 ; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
22 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
34 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
46 ; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
59 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
71 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
83 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
93 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
126 ; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
[all …]
Dllvm.AMDGPU.read.workdim.ll2 … -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -chec…
10 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
22 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
Dllvm.AMDGPU.div_fixup.ll2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
11 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
12 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
13 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
Dudivrem64.ll2 ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --chec…
71 ;VI-NOT: v_lshrrev_b64
145 ;VI-NOT: v_lshrrev_b64
160 ;VI-NOT: v_lshrrev_b64
177 ;VI-NOT: v_lshrrev_b64
195 ;VI-NOT: v_lshrrev_b64
214 ;VI-NOT: v_lshrrev_b64
Dsdivrem64.ll2 ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --chec…
71 ;VI-NOT: v_lshrrev_b64
145 ;VI-NOT: v_lshrrev_b64
160 ;VI-NOT: v_lshrrev_b64
177 ;VI-NOT: v_lshrrev_b64
197 ;VI-NOT: v_lshrrev_b64
217 ;VI-NOT: v_lshrrev_b64
Dhsa.ll2 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI --check-pre…
34 ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
48 ; On VI+ we also need to set MTYPE = 2
49 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
Dflat-scratch-reg.ll2 … -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI
22 ; VI: ; NumSgprs: 14
31 ; VI: ; NumSgprs: 14
Doperand-spacing.ll2 …nga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
9 ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
10 ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
Dimm.ll2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
324 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
335 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
346 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
357 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
368 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
379 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
390 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
401 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
412 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
[all …]
Dwork-item-intrinsics.ll2 … -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -chec…
4 …ify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=HSA -check-pre…
44 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
59 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
74 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
89 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
104 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
/external/harfbuzz_ng/src/
Dhb-ot-shape-complex-indic-table.cc102 /* 0900 */ _(Bi,T), _(Bi,T), _(Bi,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
103 /* 0908 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
104 /* 0910 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(C,x), _(C,x), _(C,x),
114 /* 0960 */ _(VI,x), _(VI,x), _(M,B), _(M,B), _(x,x), _(x,x), _(Nd,x), _(Nd,x),
116 /* 0970 */ _(x,x), _(x,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
121 /* 0980 */ _(x,x), _(Bi,T), _(Bi,R), _(Vs,R), _(x,x), _(VI,x), _(VI,x), _(VI,x),
122 /* 0988 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(x,x), _(x,x), _(VI,x),
123 /* 0990 */ _(VI,x), _(x,x), _(x,x), _(VI,x), _(VI,x), _(C,x), _(C,x), _(C,x),
133 /* 09E0 */ _(VI,x), _(VI,x), _(M,B), _(M,B), _(x,x), _(x,x), _(Nd,x), _(Nd,x),
140 /* 0A00 */ _(x,x), _(Bi,T), _(Bi,T), _(Vs,R), _(x,x), _(VI,x), _(VI,x), _(VI,x),
[all …]
/external/llvm/lib/IR/
DValueSymbolTable.cpp27 for (iterator VI = vmap.begin(), VE = vmap.end(); VI != VE; ++VI) in ~ValueSymbolTable() local
29 << *VI->getValue()->getType() << "' Name = '" in ~ValueSymbolTable()
30 << VI->getKeyData() << "'\n"; in ~ValueSymbolTable()
/external/clang/test/CodeGenCXX/
Dmangle-alias-template.cpp16 vector<int> VI; in z() local
17 f(VI); in z()
24 h<Vec>(VI); in z()

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