| /external/llvm/test/CodeGen/X86/ |
| D | vshift-6.ll | 13 ; VSELECT(r, B, count);
17 ; r = VSELECT(r, C, count);
19 ; VSELECT(r, r+r, count);
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| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| D | vselect-avx.ll | 86 ; We shouldn't try to lower this directly using VSELECT because we don't have
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 355 VSELECT, enumerator
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| D | BasicTTIImpl.h | 445 ISD = ISD::VSELECT; in getCmpSelInstrCost()
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| D | SelectionDAG.h | 746 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
98 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
275 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
320 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1091 case ISD::VSELECT: in PerformDAGCombine()
1594 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1607 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1612 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1615 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 291 case ISD::VSELECT: in LegalizeOp()
710 case ISD::VSELECT: in Expand()
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| D | LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
452 case ISD::VSELECT: in ScalarizeVectorOperand()
593 case ISD::VSELECT: in SplitVectorResult()
1424 case ISD::VSELECT: in SplitVectorOperand()
1496 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
1498 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2011 case ISD::VSELECT: in WidenVectorResult()
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| D | SelectionDAGDumper.cpp | 215 case ISD::VSELECT: return "vselect"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
577 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
891 case ISD::VSELECT: in PromoteIntegerOperand()
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| D | SelectionDAGBuilder.cpp | 2449 ISD::VSELECT : ISD::SELECT; in visitSelect()
2467 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); in visitSelect()
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| D | DAGCombiner.cpp | 1397 case ISD::VSELECT: return visitVSELECT(N); in visit()
8790 return DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, in visitFSQRT()
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| D | SelectionDAG.cpp | 6976 case ISD::VSELECT: in UnrollVectorOp()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 751 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
806 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in X86TargetLowering()
880 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
904 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom); in X86TargetLowering()
905 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom); in X86TargetLowering()
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
1282 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1291 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
1602 setOperationAction(ISD::VSELECT, VT, Legal); in X86TargetLowering()
1660 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal); in X86TargetLowering()
[all …]
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| D | X86ISelDAGToDAG.cpp | 2302 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0), in Select()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1274 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); in LowerVSELECT()
1807 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
2608 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 485 setOperationAction(ISD::VSELECT, VT, Expand); in PPCTargetLowering()
586 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
587 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
588 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
589 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
590 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
676 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in PPCTargetLowering()
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
765 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
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| D | PPCISelDAGToDAG.cpp | 2830 case ISD::VSELECT: in Select()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 324 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
363 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 456 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 502 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
677 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand); in addTypeForNEON()
9523 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
9638 case ISD::VSELECT: in PerformDAGCombine()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 286 setOperationAction(ISD::VSELECT, VT, Legal); in SystemZTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 120 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
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