| /external/pcre/dist/doc/ |
| D | pcre-config.txt | 27 --prefix Writes the directory prefix used in the PCRE installation for
32 Writes the directory prefix used in the PCRE installation for
36 --version Writes the version number of the installed PCRE libraries to
39 --libs Writes to the standard output the command line options
43 --libs16 Writes to the standard output the command line options
47 --libs32 Writes to the standard output the command line options
52 Writes to the standard output the command line options
57 Writes to the standard output the command line options
61 --cflags Writes to the standard output the command line options
66 Writes to the standard output the command line options
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 377 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
381 findRWs(WriteDefs, Writes, false); in findRWs()
503 IdxVec Writes, Reads; in collectSchedClasses() local
505 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
510 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses()
544 if (!SC.Writes.empty()) { in collectSchedClasses()
547 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI) in collectSchedClasses()
560 IdxVec Writes; in collectSchedClasses() local
563 Writes, Reads); in collectSchedClasses()
564 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) in collectSchedClasses()
[all …]
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| D | CodeGenSchedule.h | 132 IdxVec Writes; member
148 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
359 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
371 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
417 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| D | SubtargetEmitter.cpp | 865 IdxVec Writes = SCI->Writes; in GenSchedClassTables() local
880 Writes.clear(); in GenSchedClassTables()
883 Writes, Reads); in GenSchedClassTables()
886 if (Writes.empty()) { in GenSchedClassTables()
894 Writes, Reads); in GenSchedClassTables()
898 if (Writes.empty()) { in GenSchedClassTables()
908 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) { in GenSchedClassTables()
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| /external/blktrace/doc/ |
| D | blktrace.tex | 163 Reads Queued: 0, 0KiB Writes Queued: 7, 128KiB
165 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
170 Reads Queued: 0, 0KiB Writes Queued: 1, 28KiB
172 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
177 Reads Queued: 0, 0KiB Writes Queued: 11, 168KiB
179 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
299 Reads Queued: 0, 0KiB Writes Queued: 9, 5,520KiB
301 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
305 Reads Queued: 2,411, 38,576KiB Writes Queued: 769, 425,408KiB
307 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 1883 list <WriteSequence> Writes = writes;
2087 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2088 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2089 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2090 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2091 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2092 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2093 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2094 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2192 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBundle.h | 159 bool Writes; member
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| /external/deqp/doc/testspecs/GLES31/ |
| D | functional.ssbo.txt | 60 shader text. Writes are validated by reading back the SSBO and comparing
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstrBundle.cpp | 285 RI.Writes = true; in analyzeVirtReg()
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| D | InlineSpiller.cpp | 1275 if (RI.Writes) { in spillAroundUses()
1318 if (RI.Writes) in spillAroundUses()
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| D | RegisterCoalescer.cpp | 1183 bool Reads, Writes; in updateRegDefsUses() local
1184 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); in updateRegDefsUses()
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| /external/nanopb-c/docs/ |
| D | reference.rst | 395 Writes data to an output stream. Always use this function, instead of trying to call stream callbac…
494 Writes the length of a string as varint and then contents of the string. Works for fields of type `…
505 Writes 4 bytes to stream and swaps bytes on big-endian architectures. Works for fields of type `fix…
515 Writes 8 bytes to stream and swaps bytes on big-endian architecture. Works for fields of type `fixe…
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 225 list<SchedWrite> Writes = writes;
309 // to implement pipeline bypass. The Writes list may be empty to
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| /external/icu/icu4c/source/data/mappings/ |
| D | convrtrs.txt | 245 # From Unicode: Writes BOM.
256 # From Unicode: Writes BOM.
269 # From Unicode: Writes BOM.
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| /external/mesa3d/src/gallium/docs/source/ |
| D | context.rst | 137 by the shader resource. Writes to a shader resource are only allowed
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| /external/selinux/policycoreutils/po/ |
| D | no.po | 1750 msgid "Writes syslog messages\t"
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| D | wo.po | 1750 msgid "Writes syslog messages\t"
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| D | zh_HK.po | 1749 msgid "Writes syslog messages\t"
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| D | ro.po | 1751 msgid "Writes syslog messages\t"
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| D | cy.po | 1751 msgid "Writes syslog messages\t"
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| D | ku.po | 1750 msgid "Writes syslog messages\t"
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| D | bo.po | 1749 msgid "Writes syslog messages\t"
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| D | lo.po | 1750 msgid "Writes syslog messages\t"
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| D | xh.po | 1750 msgid "Writes syslog messages\t"
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| D | hr_HR.po | 1751 msgid "Writes syslog messages\t"
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