| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 821 ZEXTLOAD, enumerator
|
| D | SelectionDAGNodes.h | 2287 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
147 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
560 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerParameter()
1685 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
|
| D | R600ISelLowering.cpp | 138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
1507 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
|
| D | AMDGPUISelLowering.cpp | 187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
193 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
196 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
202 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
|
| D | AMDGPUInstructions.td | 189 return L->getExtensionType() == ISD::ZEXTLOAD ||
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 968 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1190 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
2984 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
3001 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
3004 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
3145 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
3159 case ISD::ZEXTLOAD: in visitAND()
3168 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
3211 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3239 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
[all …]
|
| D | LegalizeDAG.cpp | 549 HiExtType = ISD::ZEXTLOAD; in ExpandUnalignedLoad()
554 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in ExpandUnalignedLoad()
572 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in ExpandUnalignedLoad()
985 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1000 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1026 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
1067 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeLoadOps()
1150 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT, in LegalizeLoadOps()
|
| D | SelectionDAGDumper.cpp | 503 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
|
| D | LegalizeVectorOps.cpp | 602 case ISD::ZEXTLOAD: in ExpandLoad()
|
| D | LegalizeIntegerTypes.cpp | 2031 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
2081 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 186 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 130 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
134 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
465 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 242 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
275 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
1603 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) { in adjustSubwordCmp()
1614 ISD::ZEXTLOAD); in adjustSubwordCmp()
1643 case ISD::ZEXTLOAD: in isNaturalMemoryOperand()
1796 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || in adjustICmpTruncate()
|
| D | SystemZOperators.td | 388 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
419 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2229 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
3742 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 231 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
2172 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
2298 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 757 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal); in X86TargetLowering()
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); in X86TargetLowering()
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal); in X86TargetLowering()
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal); in X86TargetLowering()
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal); in X86TargetLowering()
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal); in X86TargetLowering()
1218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal); in X86TargetLowering()
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal); in X86TargetLowering()
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal); in X86TargetLowering()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 381 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
|
| D | HexagonISelLowering.cpp | 1297 Ext = ISD::ZEXTLOAD; in LowerLOAD()
1707 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
|
| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 4176 LType = ISD::ZEXTLOAD; in moveExtToFormExtLoad()
4423 !TLI->isLoadExtLegal(ISD::ZEXTLOAD, LoadResultVT, TruncVT)) in optimizeLoadExt()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
493 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
2314 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2337 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
6447 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
11466 LD->getExtensionType() == ISD::ZEXTLOAD)) in isZExtFree()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1457 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1461 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
|