/external/llvm/test/CodeGen/SystemZ/ |
D | and-02.ll | 10 %and = and i32 %a, 1 11 ret i32 %and 19 %and = and i32 %b, 1 20 ret i32 %and 28 %and = and i32 %b, 4 29 ret i32 %and 37 %and = and i32 %a, 5 38 ret i32 %and 46 %and = and i32 %b, 5 47 ret i32 %and [all …]
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D | and-04.ll | 10 %and = and i64 %a, 1 11 ret i64 %and 19 %and = and i64 %a, 65534 20 ret i64 %and 28 %and = and i64 %b, 65535 29 ret i64 %and 37 %and = and i64 %a, 65536 38 ret i64 %and 46 %and = and i64 %a, 4294967294 47 ret i64 %and [all …]
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D | risbg-01.ll | 12 %and = and i32 %shr, 1 13 ret i32 %and 16 ; ...and again with i64. 22 %and = and i64 %shr, 1 23 ret i64 %and 32 %and = and i32 %shr, 12 33 ret i32 %and 36 ; ...and again with i64. 42 %and = and i64 %shr, 12 43 ret i64 %and [all …]
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D | rnsbg-01.ll | 11 %and = and i32 %a, %orb 12 ret i32 %and 15 ; ...and again with i64. 21 %and = and i64 %a, %orb 22 ret i64 %and 31 %and = and i32 %a, %orb 32 ret i32 %and 35 ; ...and again with i64. 41 %and = and i64 %a, %orb 42 ret i64 %and [all …]
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D | insert-04.ll | 12 %and = and i64 %a, 18446744073709486080 13 %or = or i64 %and, 1 23 %and = and i64 %a, -65536 24 %or = or i64 %and, 32769 35 %and = and i64 %a, 18446744073709486080 36 %or = or i64 %and, 65534 46 %and = and i64 %a, 18446744069414649855 47 %or = or i64 %and, 65536 57 %and = and i64 %a, -4294901761 58 %or = or i64 %and, 2147418112 [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | tbi.ll | 7 ; TBI-NOT: and x 8 ; NO_TBI: and x 10 %and = and i64 %p, 72057594037927935 11 %cast = inttoptr i64 %and to i32* 18 ; TBI-NOT: and x 19 ; NO_TBI: and x 21 %and = and i64 %p, 72057594037927935 22 %cast = inttoptr i64 %and to i32* 30 ; TBI-NOT: and x 31 ; NO_TBI: and x [all …]
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/external/llvm/test/Transforms/InstCombine/ |
D | bit-checks.ll | 8 %and = and i32 %argc, 1 ; <i32> [#uses=1] 9 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1] 10 %and2 = and i32 %argc, 2 ; <i32> [#uses=1] 12 %or.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1] 19 %and = and i32 %argc, 1 ; <i32> [#uses=1] 20 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1] 21 %and2 = and i32 %argc, 2 ; <i32> [#uses=1] 35 %and = and i32 %argc, 7 ; <i32> [#uses=1] 36 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1] 37 %and2 = and i32 %argc, 48 ; <i32> [#uses=1] [all …]
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D | and2.ll | 7 %bothcond = and i1 %tmp13, %tmp9 13 %a = and i1 %X, %Y 14 %b = and i1 %a, %X 17 ; CHECK-NEXT: and i1 %X, %Y 22 %a = and i32 %X, %Y 23 %b = and i32 %Y, %a 26 ; CHECK-NEXT: and i32 %X, %Y 33 %c = and i1 %a, %b 42 %2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1 53 %.cmp1 = and i1 %cmp1, %not.cmp [all …]
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D | icmp-logical.ll | 5 ; CHECK: [[MASK:%.*]] = and i32 %A, 7 7 ; CHECK-NOT: and i32 %A, 39 10 %mask1 = and i32 %A, 7 13 %mask2 = and i32 %A, 39 16 %res = and i1 %tst1, %tst2 22 ; CHECK: [[MASK:%.*]] = and i32 %A, 7 24 ; CHECK-NOT: and i32 %A, 39 27 %mask1 = and i32 %A, 7 30 %mask2 = and i32 %A, 39 39 ; CHECK: [[MASK:%.*]] = and i32 %A, 7 [all …]
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D | bitreverse-recognize.ll | 12 %3 = and i8 %2, 64 14 %5 = and i8 %4, 32 16 %7 = and i8 %6, 16 18 %9 = and i8 %8, 8 20 %11 = and i8 %10, 4 22 %13 = and i8 %12, 2 34 ; The ANDs with 32 and 64 have been swapped here, so the sequence does not 42 %3 = and i8 %2, 32 44 %5 = and i8 %4, 64 46 %7 = and i8 %6, 16 [all …]
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/external/icu/icu4c/source/data/rbnf/ |
D | mt.txt | 4 // * Corporation and others. All Rights Reserved. 81 "1000: elf[>%%and-type-b-masculine>];", 82 "2000: elfejn[>%%and-type-b-masculine>];", 83 "3000: <%%thousands< elef[>%%and-type-b-masculine>];", 84 "11000/1000: <%spellout-cardinal-masculine< elf[>%%and-type-b-masculine>];", 85 "1000000: miljun[>%%and-type-b-masculine>];", 86 "2000000: <%spellout-cardinal-masculine< miljuni[>%%and-type-b-masculine>];", 87 "11000000/1,000: <%spellout-cardinal-masculine< miljun[>%%and-type-b-masculine>];", 88 "1000000000: biljun[>%%and-type-b-masculine>];", 89 "2000000000: <%spellout-cardinal-masculine< biljuni[>%%and-type-b-masculine>];", [all …]
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D | he.txt | 4 // * Corporation and others. All Rights Reserved. 32 "20: \u05E2\u05E9\u05E8\u05D9\u05DD[ >%%and-feminine>];", 33 "30: \u05E9\u05DC\u05D5\u05E9\u05D9\u05DD[ >%%and-feminine>];", 34 "40: \u05D0\u05E8\u05D1\u05E2\u05D9\u05DD[ >%%and-feminine>];", 35 "50: \u05D7\u05DE\u05D9\u05E9\u05D9\u05DD[ >%%and-feminine>];", 36 "60: \u05E9\u05D9\u05E9\u05D9\u05DD[ >%%and-feminine>];", 37 "70: \u05E9\u05D1\u05E2\u05D9\u05DD[ >%%and-feminine>];", 38 "80: \u05E9\u05DE\u05D5\u05E0\u05D9\u05DD[ >%%and-feminine>];", 39 "90: \u05EA\u05E9\u05E2\u05D9\u05DD[ >%%and-feminine>];", 40 "100: \u05DE\u05D0\u05D4[ >%%and-feminine>];", [all …]
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/external/llvm/test/Transforms/InstSimplify/ |
D | select.ll | 4 %and = and i32 %x, 1 5 %cmp = icmp eq i32 %and, 0 6 %and1 = and i32 %x, -2 14 %and = and i32 %x, 1 15 %cmp = icmp ne i32 %and, 0 16 %and1 = and i32 %x, -2 24 %and = and i32 %x, 1 25 %cmp = icmp ne i32 %and, 0 26 %and1 = and i32 %x, -2 30 ; CHECK: %[[and:.*]] = and i32 %x, -2 [all …]
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/external/opencv3/doc/ |
D | opencv.bib | 7 author = {Alcantarilla, Pablo Fern{\'a}ndez and Bartoli, Adrien and Davison, Andrew J}, 15 author = {Alcantarilla, Pablo F and Nuevo, Jes{\'u}s and Bartoli, Adrien}, 24 author = {Burt, Peter J and Adelson, Edward H}, 34 author = {Brown, Matthew and Lowe, David G}, 44 author = {Birchfield, Stan and Tomasi, Carlo}, 54 author = {Birchfield, Stan and Tomasi, Carlo}, 58 journal = {Pattern Analysis and Machine Intelligence, IEEE Transactions on}, 78 journal = {Computer vision, graphics, and image processing}, 96 author = {Bradski, GR and Davis, J}, 97 title = {Motion segmentation and pose recognition with motion history gradients}, [all …]
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/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/duration/testdata/ |
D | testdata_en.txt | 167 1 hour and 5 minutes 169 1 hour and 10 minutes 171 1 hour and 15 minutes 173 1 hour and 20 minutes 175 1 hour and 25 minutes 177 1 hour and 30 minutes 179 1 hour and 35 minutes 181 1 hour and 40 minutes 183 1 hour and 45 minutes 185 1 hour and 50 minutes [all …]
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/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/duration/testdata/ |
D | testdata_en.txt | 167 1 hour and 5 minutes 169 1 hour and 10 minutes 171 1 hour and 15 minutes 173 1 hour and 20 minutes 175 1 hour and 25 minutes 177 1 hour and 30 minutes 179 1 hour and 35 minutes 181 1 hour and 40 minutes 183 1 hour and 45 minutes 185 1 hour and 50 minutes [all …]
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/external/llvm/test/CodeGen/PowerPC/ |
D | bperm.ll | 44 %and = and i64 %0, 5963776000 45 ret i64 %and 51 ; CHECK: and 3, [[REG3]], [[REG2]] 58 %and = and i64 %0, 133434808670355456 59 ret i64 %and 67 ; CHECK: and 3, [[REG5]], [[REG4]] 74 %and = and i64 %0, 191795733152661504 75 ret i64 %and 82 ; CHECK: and 3, [[REG4]], [[REG3]] 89 %and = and i64 %0, 58195968 [all …]
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/external/llvm/test/CodeGen/X86/ |
D | rotate4.ll | 8 ; CHECK-NOT: and 11 %and = and i32 %b, 31 12 %shl = shl i32 %a, %and 14 %and3 = and i32 %0, 31 22 ; CHECK-NOT: and 25 %and = and i32 %b, 31 26 %shl = lshr i32 %a, %and 28 %and3 = and i32 %0, 31 36 ; CHECK-NOT: and 39 %and = and i64 %b, 63 [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | bfi.ll | 13 %1 = and i32 %0, -62914561 ; <i32> [#uses=1] 24 %and = and i32 %A, -8388481 ; <i32> [#uses=1] 25 %and2 = and i32 %B, 8388480 ; <i32> [#uses=1] 26 %or = or i32 %and2, %and ; <i32> [#uses=1] 35 %and = and i32 %A, 8388480 ; <i32> [#uses=1] 36 %and2 = and i32 %B, -8388481 ; <i32> [#uses=1] 37 %or = or i32 %and2, %and ; <i32> [#uses=1] 47 %ins7 = and i32 %1, 1015808 58 %0 = and i32 %a, -15728641 60 %2 = and i32 %1, 15728640 [all …]
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/external/v8/build/config/win/ |
D | msvs_dependencies.isolate | 11 …['OS=="win" and msvs_version==2013 and component=="shared_library" and CONFIGURATION_NAME=="Debug"… 19 …['OS=="win" and msvs_version==2013 and component=="shared_library" and CONFIGURATION_NAME=="Releas… 27 …['OS=="win" and msvs_version==2013 and component=="shared_library" and (CONFIGURATION_NAME=="Debug… 35 …['OS=="win" and msvs_version==2013 and component=="shared_library" and (CONFIGURATION_NAME=="Relea… 44 …['OS=="win" and msvs_version==2015 and component=="shared_library" and CONFIGURATION_NAME=="Debug"… 52 …['OS=="win" and msvs_version==2015 and component=="shared_library" and CONFIGURATION_NAME=="Releas… 60 …['OS=="win" and msvs_version==2015 and component=="shared_library" and (CONFIGURATION_NAME=="Debug… 68 …['OS=="win" and msvs_version==2015 and component=="shared_library" and (CONFIGURATION_NAME=="Relea…
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/external/llvm/test/CodeGen/AMDGPU/ |
D | and.ll | 18 %result = and <2 x i32> %a, %b 38 %result = and <4 x i32> %a, %b 46 %and = and i32 %a, %b 47 store i32 %and, i32 addrspace(1)* %out, align 4 54 %and = and i32 %a, 1234567 55 store i32 %and, i32 addrspace(1)* %out, align 4 60 ; can fold into the s_and_b32 and the VALU one is materialized 70 %and = and i32 %a, 1234567 73 %foo = add i32 %and, %b 87 %and = and i32 %a, 1234567 [all …]
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/external/llvm/test/MC/Mips/ |
D | mips64extins.ll | 9 %and = and i64 %shr, 1023 10 ret i64 %and 17 %and = and i64 %shr, 63 18 ret i64 %and 25 %and = and i64 %shr, 17179869183 26 ret i64 %and 33 %and = and i64 %shl2, 261888 34 %and3 = and i64 %i, -261889 35 %or = or i64 %and3, %and 43 %and = and i64 %shl4, 8796093021184 [all …]
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/external/llvm/test/CodeGen/Mips/ |
D | mips64extins.ll | 7 %and = and i64 %shr, 1023 8 ret i64 %and 15 %and = and i64 %shr, 17179869183 16 ret i64 %and 23 %and = and i64 %shr, 63 24 ret i64 %and 31 %and = and i64 %shl2, 261888 32 %and3 = and i64 %i, -261889 33 %or = or i64 %and3, %and 41 %and = and i64 %shl4, 8796093021184 [all …]
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/external/valgrind/ |
D | AUTHORS | 2 Julian Seward was the original founder, designer and author of 4 the 3.X versions of Helgrind, SGCheck, DHAT, and did lots of other 8 Cachegrind and Massif, and tons of other stuff. 11 more recent Linux/glibc versions, set up the present build system, and has 12 helped out with test and build machines. 14 Jeremy Fitzhardinge wrote Helgrind (in the 2.X line) and totally 15 overhauled low-level syscall/signal and address space layout stuff, 18 Josef Weidendorfer wrote and maintains Callgrind and the associated 22 that forms the basis of the 3.0 line and was also seen in 2.4.0. 23 He also did UCode-based dynamic translation support for PowerPC, and [all …]
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/external/v8/ |
D | ChangeLog | 3 Performance and stability improvements on all platforms. 8 Performance and stability improvements on all platforms. 13 Performance and stability improvements on all platforms. 18 Performance and stability improvements on all platforms. 23 Performance and stability improvements on all platforms. 28 Performance and stability improvements on all platforms. 33 Performance and stability improvements on all platforms. 38 Performance and stability improvements on all platforms. 43 Performance and stability improvements on all platforms. 48 Performance and stability improvements on all platforms. [all …]
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