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Searched refs:createReg (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
756 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp184 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
252 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
256 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
277 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
543 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
546 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
549 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
552 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); in translateImmediate()
585 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
618 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp762 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
771 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
772 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
781 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
782 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
783 TmpInst.addOperand(MCOperand::createReg(RegNo)); in emitDirectiveCpLoad()
822 Inst.addOperand(MCOperand::createReg(RegOrOffset)); in emitDirectiveCpsetup()
823 Inst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpsetup()
824 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in emitDirectiveCpsetup()
828 Inst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpsetup()
[all …]
DMipsNaClELFStreamer.cpp97 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
98 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
99 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass()
578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass()
602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass()
620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass()
1386 Op = MCOperand::createReg(operand); in addSubinstOperands()
1389 Op = MCOperand::createReg(operand); in addSubinstOperands()
1397 Op = MCOperand::createReg(operand); in addSubinstOperands()
1400 Op = MCOperand::createReg(operand); in addSubinstOperands()
1408 Op = MCOperand::createReg(operand); in addSubinstOperands()
1411 Op = MCOperand::createReg(operand); in addSubinstOperands()
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DThumb1InstrInfo.cpp30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoopForMachoTarget()
31 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoopForMachoTarget()
33 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DARMAsmPrinter.cpp1379 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1400 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1402 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1411 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1412 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); in EmitInstruction()
1432 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1434 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1591 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1592 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1595 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp55 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
255 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
265 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
267 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
277 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
289 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDVAddr12Operand()
291 Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index])); in decodeBDVAddr12Operand()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1687 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1717 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
1722 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
1729 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1739 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1757 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
1966 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
1993 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
2056 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h386 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
417 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
430 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
432 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
434 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
448 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
449 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
453 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
463 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOffsOperands()
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp470 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
503 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
509 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()
510 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
517 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
518 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
532 Blr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
151 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
190 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
199 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
208 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
217 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
232 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp211 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
334 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
341 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
346 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
362 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
364 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
367 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
378 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp414 return MCOperand::createReg(MO.getReg()); in LowerMachineOperand()
549 OutMI.addOperand(MCOperand::createReg(ReturnReg)); in Lower()
748 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest in LowerTlsAddr()
749 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base in LowerTlsAddr()
751 LEA.addOperand(MCOperand::createReg(0)); // index in LowerTlsAddr()
753 LEA.addOperand(MCOperand::createReg(0)); // seg in LowerTlsAddr()
756 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest in LowerTlsAddr()
757 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base in LowerTlsAddr()
759 LEA.addOperand(MCOperand::createReg(0)); // index in LowerTlsAddr()
761 LEA.addOperand(MCOperand::createReg(0)); // seg in LowerTlsAddr()
[all …]
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() function in __anon2bc5d5650111::SystemZOperand
256 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDVAddrOperands()
258 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDVAddrOperands()
270 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
284 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDAddrOperands()
290 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDXAddrOperands()
292 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDXAddrOperands()
297 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDLAddrOperands()
567 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, in parseRegister()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp272 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
301 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
322 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
343 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
364 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
385 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
397 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
418 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
431 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass()
452 Inst.addOperand(MCOperand::createReg(Register)); in DecodeVectorRegisterClass()
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp826 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); in addGPR32AsmRegOperands()
831 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegOperands()
836 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegZeroOperands()
841 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegMovePOperands()
849 Inst.addOperand(MCOperand::createReg(getGPR64Reg())); in addGPR64AsmRegOperands()
854 Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); in addAFGR64AsmRegOperands()
859 Inst.addOperand(MCOperand::createReg(getFGR64Reg())); in addFGR64AsmRegOperands()
864 Inst.addOperand(MCOperand::createReg(getFGR32Reg())); in addFGR32AsmRegOperands()
873 Inst.addOperand(MCOperand::createReg(getFGRH32Reg())); in addFGRH32AsmRegOperands()
878 Inst.addOperand(MCOperand::createReg(getFCCReg())); in addFCCAsmRegOperands()
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
786 I.addOperand(MCOperand::createReg(Reg)); in EmitInstrReg()
805 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
806 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
815 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
816 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
817 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp403 TmpInst.addOperand(MCOperand::createReg(High)); in HexagonProcessInstruction()
404 TmpInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
489 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
501 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
514 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
644 MI.insert(I, MCOperand::createReg(0)); in AddThumbPredicate()
646 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
654 MI.insert(I, MCOperand::createReg(0)); in AddThumbPredicate()
656 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
877 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
901 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
932 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
962 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
578 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
583 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
588 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
593 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
598 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
603 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
[all …]
/external/llvm/include/llvm/MC/
DMCInstBuilder.h33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
/external/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp59 MCOp = MCOperand::createReg(MO.getReg()); in Lower()
/external/llvm/lib/Target/Sparc/
DSparcMCInstLower.cpp77 return MCOperand::createReg(MO.getReg()); in LowerOperand()

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