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Searched refs:dst_rel (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Dr600_asm.h72 unsigned dst_rel; member
Dr600_asm.c1742 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) | in r600_bytecode_tex_build()
2541 fprintf(stderr, "REL:%d ", tex->dst_rel); in r600_bytecode_dump()
Dr600_shader.c449 tex.dst_rel = bytes[bytes_read++]; in r600_tex_from_byte_stream()
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td108 bits<1> dst_rel;
116 let Word1{28} = dst_rel;
DR600Instructions.td96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
101 "$clamp $last $dst$write$dst_rel$omod, "
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
177 (ins REL:$dst_rel, CLAMP:$clamp,
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
DR600InstrInfo.cpp1133 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1); in buildIndirectWrite()
1234 OPERAND_CASE(AMDGPU::OpName::dst_rel) in getSlotedOps()
1275 AMDGPU::OpName::dst_rel, in buildSlotOfVectorInstruction()
DEvergreenInstructions.td380 let dst_rel = 0;