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/external/valgrind/none/tests/s390x/
Dpfpo.stdout.exp21 f128 -> d32: round=0 1234567812345678912345678912.565679 -> 27a4d2e8 ret=0 cc=1
22 f128 -> d32: round=0 0.000000 -> 0 ret=0 cc=1
23 f128 -> d32: round=0 118973149535723176508575932662800701619646905264169404552969888421216357975531…
24 f128 -> d6: round=0 1234567812345678912345678912.565679 -> 266934b9d1c71779 ret=0 cc=1
25 f128 -> d6: round=0 0.000000 -> 0 ret=0 cc=1
26 f128 -> d6: round=0 1189731495357231765085759326628007016196469052641694045529698884212163579755312…
27 f128 -> d128: round=0 1234567812345678912345678912.565679 -> 2606934b9d1c71778671c5de19cb9779 ret=0…
28 f128 -> d128: round=0 0.000000 -> d2ede220cc32483ba1962ddf1d687d3 ret=0 cc=1
29 f128 -> d128: round=0 11897314953572317650857593266280070161964690526416940455296988842121635797553…
75 f128 -> d32: round=1 1234567812345678912345678912.565679 -> 27a4d2e8 ret=0 cc=1
[all …]
Dfpext.c57 long double f128; \
58 printf(#insn " %Lf\n", L2F(insn, 0, f128, round)); \
59 printf(#insn " %Lf\n", L2F(insn, 1, f128, round)); \
60 printf(#insn " %Lf\n", L2F(insn, 0xffffffffUL, f128, round)); \
61 printf(#insn " %Lf\n", L2F(insn, 0x80000000UL, f128, round)); \
62 printf(#insn " %Lf\n", L2F(insn, 0x7fffffffUL, f128, round)); \
63 printf(#insn " %Lf\n", L2F(insn, 0x100000000UL, f128, round)); \
64 printf(#insn " %Lf\n", L2F(insn, 0xffffffffffffffffUL, f128, round)); \
65 printf(#insn " %Lf\n", L2F(insn, 0x8000000000000000UL, f128, round)); \
66 printf(#insn " %Lf\n", L2F(insn, 0x7fffffffffffffffUL, f128, round)); \
Dpfpo.c55 long double f128; in main() local
199 f128 = PFPO(d32_in[j], _Decimal32, long double, PFPO_D32_TO_F128, in main()
201 printf("%Lf", f128); in main()
232 f128 = PFPO(d64_in[j], _Decimal64, long double, PFPO_D64_TO_F128, in main()
234 printf("%Lf", f128); in main()
265 f128 = PFPO(d128_in[j], _Decimal128, long double, PFPO_D128_TO_F128, in main()
267 printf("%Lf", f128); in main()
/external/llvm/test/CodeGen/AArch64/
Dillegal-float-ops.ll9 declare fp128 @llvm.cos.f128(fp128)
22 %cosfp128 = call fp128 @llvm.cos.f128(fp128 %fp128)
31 declare fp128 @llvm.exp.f128(fp128)
44 %expfp128 = call fp128 @llvm.exp.f128(fp128 %fp128)
53 declare fp128 @llvm.exp2.f128(fp128)
66 %exp2fp128 = call fp128 @llvm.exp2.f128(fp128 %fp128)
75 declare fp128 @llvm.log.f128(fp128)
88 %logfp128 = call fp128 @llvm.log.f128(fp128 %fp128)
97 declare fp128 @llvm.log2.f128(fp128)
110 %log2fp128 = call fp128 @llvm.log2.f128(fp128 %fp128)
[all …]
Darm64-illegal-float-ops.ll9 declare fp128 @llvm.cos.f128(fp128)
22 %cosfp128 = call fp128 @llvm.cos.f128(fp128 %fp128)
31 declare fp128 @llvm.exp.f128(fp128)
44 %expfp128 = call fp128 @llvm.exp.f128(fp128 %fp128)
53 declare fp128 @llvm.exp2.f128(fp128)
66 %exp2fp128 = call fp128 @llvm.exp2.f128(fp128 %fp128)
75 declare fp128 @llvm.log.f128(fp128)
88 %logfp128 = call fp128 @llvm.log.f128(fp128 %fp128)
97 declare fp128 @llvm.log2.f128(fp128)
110 %log2fp128 = call fp128 @llvm.log2.f128(fp128 %fp128)
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/external/llvm/test/CodeGen/SystemZ/
Dfp-round-02.ll29 ; Test rint for f128.
30 declare fp128 @llvm.rint.f128(fp128 %f)
36 %res = call fp128 @llvm.rint.f128(fp128 %src)
61 ; Test nearbyint for f128.
62 declare fp128 @llvm.nearbyint.f128(fp128 %f)
68 %res = call fp128 @llvm.nearbyint.f128(fp128 %src)
93 ; Test floor for f128.
94 declare fp128 @llvm.floor.f128(fp128 %f)
100 %res = call fp128 @llvm.floor.f128(fp128 %src)
125 ; Test ceil for f128.
[all …]
Dfp-libcall.ll22 %tmp = call fp128 @llvm.powi.f128(fp128 %x, i32 %y)
43 %tmp = call fp128 @llvm.pow.f128(fp128 %x, fp128 %y)
64 %tmp = call fp128 @llvm.sin.f128(fp128 %x)
85 %tmp = call fp128 @llvm.cos.f128(fp128 %x)
106 %tmp = call fp128 @llvm.exp.f128(fp128 %x)
127 %tmp = call fp128 @llvm.exp2.f128(fp128 %x)
148 %tmp = call fp128 @llvm.log.f128(fp128 %x)
169 %tmp = call fp128 @llvm.log2.f128(fp128 %x)
190 %tmp = call fp128 @llvm.log10.f128(fp128 %x)
211 %tmp = call fp128 @llvm.minnum.f128(fp128 %x, fp128 %y)
[all …]
Dfp-round-01.ll25 ; Test rint for f128.
26 declare fp128 @llvm.rint.f128(fp128 %f)
32 %res = call fp128 @llvm.rint.f128(fp128 %src)
57 ; Test nearbyint for f128: omitted for now because we cannot handle
80 ; Test floor for f128: omitted for now because we cannot handle
103 ; Test ceil for f128: omitted for now because we cannot handle
126 ; Test trunc for f128: omitted for now because we cannot handle
149 ; Test round for f128: omitted for now because we cannot handle
Dfp-abs-01.ll26 ; Test f128. With the loads and stores, a pure absolute would probably
29 declare fp128 @llvm.fabs.f128(fp128 %f)
36 %abs = call fp128 @llvm.fabs.f128(fp128 %orig)
Dfp-abs-02.ll28 ; Test f128. With the loads and stores, a pure negative-absolute would
31 declare fp128 @llvm.fabs.f128(fp128 %f)
38 %abs = call fp128 @llvm.fabs.f128(fp128 %orig)
Dfp-sqrt-03.ll5 declare fp128 @llvm.sqrt.f128(fp128 %f)
17 %sqrt = call fp128 @llvm.sqrt.f128(fp128 %orig)
Dfp-conv-01.ll18 ; Test f128->f32.
43 ; Test f128->f64.
53 ; Like f3, but for f128->f64.
Dfp-copysign-01.ll31 ; Test f32 copies in which the sign comes from an f128.
65 ; Test f64 copies in which the sign comes from an f128.
78 ; Test f128 copies in which the sign comes from an f32. We shouldn't
112 ; As above, but the sign comes from an f128. Don't require the low part
Dfp-conv-14.ll23 ; Test f128->i32.
53 ; Test f128->i64.
Dfp-conv-13.ll24 ; Check i32->f128.
54 ; Check i64->f128.
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
113 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
126 else if (LocVT == MVT::f128 && Offset < 16*8) in CC_Sparc64_Full()
525 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
1071 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1094 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1178 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1185 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1441 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
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DSparcInstrInfo.td397 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
418 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
445 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
486 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
959 [(set f128:$rd, (fextend f32:$rs2))]>,
968 [(set f128:$rd, (fextend f64:$rs2))]>,
973 [(set f32:$rd, (fround f128:$rs2))]>,
978 [(set f64:$rd, (fround f128:$rs2))]>,
1007 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1024 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
[all …]
/external/llvm/test/Transforms/ConstProp/
Dconvert-from-fp16.ll34 %0 = call fp128 @llvm.convert.from.fp16.f128(i16 0)
78 %1 = call fp128 @llvm.convert.from.fp16.f128(i16 %0)
96 declare fp128 @llvm.convert.from.fp16.f128(i16)
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp447 if (RetVT == MVT::f128) in getFPEXT()
450 if (RetVT == MVT::f128) in getFPEXT()
467 if (OpVT == MVT::f128) in getFPROUND()
476 if (OpVT == MVT::f128) in getFPROUND()
483 if (OpVT == MVT::f128) in getFPROUND()
516 } else if (OpVT == MVT::f128) { in getFPTOSINT()
558 } else if (OpVT == MVT::f128) { in getFPTOUINT()
586 if (RetVT == MVT::f128) in getSINTTOFP()
597 if (RetVT == MVT::f128) in getSINTTOFP()
608 if (RetVT == MVT::f128) in getSINTTOFP()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td109 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
200 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
204 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
398 // f128 multiplication of two FP64 registers.
400 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
401 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
404 // f128 multiplication of an FP64 register and an f64 memory.
406 def : Pat<(fmul (f128 (fextend FP64:$src1)),
407 (f128 (extloadf64 bdxaddr12only:$addr))),
408 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
[all …]
/external/llvm/lib/Target/Mips/
DMipsCallingConv.td46 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
51 // For hard-float, f128 values are returned as a pair of f64's rather than a
183 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
189 // whether the result was originally an f128 into the tablegen-erated code.
191 // f128 should only occur for the N64 ABI where long double is 128-bit. On
364 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
365 // f128 is not legal and is lowered to i128 which is further lowered to a pair
370 // whether the argument was originally an f128 into the tablegen-erated code.
372 // f128 should only occur for the N64 ABI where long double is 128-bit. On
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td34 CCBitConvertToType<f128>>>,
73 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
81 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
94 CCBitConvertToType<f128>>>,
109 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
169 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
/external/llvm/test/CodeGen/PowerPC/
Dlongdbl-truncate.ll2 …8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
Dunwind-dw2.ll2 …:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:12…
Dasm-Zy.ll1 …:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:12…

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