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Searched refs:f24 (Results 1 – 25 of 144) sorted by relevance

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/external/v8/test/mjsunit/es6/regress/
Dregress-3741.js7 function f24(deopt) { function
23 f24(12);
25 %OptimizeFunctionOnNextCall(f24);
26 f24({});
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
62 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
68 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
62 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
68 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
56 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
62 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
68 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/external/llvm/test/MC/Disassembler/Mips/mips32r3/
Dvalid-xfail-mips32r3.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r5/
Dvalid-xfail-mips32r5.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r2/
Dvalid-xfail-mips32r2.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-xfail-mips4.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
38 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-xfail.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
71 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
75 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
/external/valgrind/none/tests/mips32/
DMoveIns.c307 TESTINSNMOVE("mfc1 $t9, $f24", 28, f24, t9); in main()
336 TESTINSNMOVEt("mtc1 $t9, $f24", 30, f24, t9); in main()
365 TESTINSNMOVE1s("mov.s $f23, $f24", 28, f23, f24); in main()
366 TESTINSNMOVE1s("mov.s $f24, $f25", 32, f24, f25); in main()
393 TESTINSNMOVE1d("mov.d $f22, $f24", 40, f22, f24); in main()
394 TESTINSNMOVE1d("mov.d $f22, $f24", 48, f22, f24); in main()
395 TESTINSNMOVE1d("mov.d $f24, $f26", 56, f24, f26); in main()
396 TESTINSNMOVE1d("mov.d $f24, $f26", 64, f24, f26); in main()
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll10 …3},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f2…
31 …3},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f2…
51 …3},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f2…
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips32r2.s8 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
26 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s12 add.s $f8,$f21,$f24
57 cvt.l.d $f24,$f15
63 cvt.w.s $f20,$f24
147 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
187 nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
189 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s12 add.s $f8,$f21,$f24
57 cvt.l.d $f24,$f15
63 cvt.w.s $f20,$f24
146 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
186 nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
188 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s12 add.s $f8,$f21,$f24
59 cvt.l.d $f24,$f15
65 cvt.w.s $f20,$f24
158 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
203 nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
205 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
60 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
90 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
118 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
/external/llvm/test/MC/ARM/
Dsymbol-variants.s82 .word f24(TLSDESC)
84 @ CHECK: 60 R_ARM_TLS_GOTDESC f24
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s12 add.s $f8,$f21,$f24
56 cvt.l.d $f24,$f15
61 cvt.w.s $f20,$f24
109 mfhc1 $s8,$f24
153 nmsub.s $f1,$f24,$f19,$f4
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s12 add.s $f8,$f21,$f24
56 cvt.l.d $f24,$f15
61 cvt.w.s $f20,$f24
108 mfhc1 $s8,$f24
152 nmsub.s $f1,$f24,$f19,$f4
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s12 add.s $f8,$f21,$f24
56 cvt.l.d $f24,$f15
61 cvt.w.s $f20,$f24
108 mfhc1 $s8,$f24
152 nmsub.s $f1,$f24,$f19,$f4
/external/v8/test/cctest/
Dtest-disasm-mips64.cc1238 COMPARE(cvt_d_s(f22, f24), "4600c5a1 cvt.d.s f22, f24"); in TEST()
1239 COMPARE(cvt_d_w(f22, f24), "4680c5a1 cvt.d.w f22, f24"); in TEST()
1241 COMPARE(cvt_d_l(f22, f24), "46a0c5a1 cvt.d.l f22, f24"); in TEST()
1245 COMPARE(cvt_l_s(f22, f24), "4600c5a5 cvt.l.s f22, f24"); in TEST()
1246 COMPARE(cvt_l_d(f22, f24), "4620c5a5 cvt.l.d f22, f24"); in TEST()
1249 COMPARE(cvt_s_d(f22, f24), "4620c5a0 cvt.s.d f22, f24"); in TEST()
1250 COMPARE(cvt_s_w(f22, f24), "4680c5a0 cvt.s.w f22, f24"); in TEST()
1252 COMPARE(cvt_s_l(f22, f24), "46a0c5a0 cvt.s.l f22, f24"); in TEST()
1255 COMPARE(cvt_s_d(f22, f24), "4620c5a0 cvt.s.d f22, f24"); in TEST()
1256 COMPARE(cvt_s_w(f22, f24), "4680c5a0 cvt.s.w f22, f24"); in TEST()
Dtest-disasm-mips.cc1054 COMPARE(cvt_d_s(f22, f24), "4600c5a1 cvt.d.s f22, f24"); in TEST()
1055 COMPARE(cvt_d_w(f22, f24), "4680c5a1 cvt.d.w f22, f24"); in TEST()
1057 COMPARE(cvt_s_d(f22, f24), "4620c5a0 cvt.s.d f22, f24"); in TEST()
1058 COMPARE(cvt_s_w(f22, f24), "4680c5a0 cvt.s.w f22, f24"); in TEST()
1062 COMPARE(cvt_d_l(f22, f24), "46a0c5a1 cvt.d.l f22, f24"); in TEST()
1063 COMPARE(cvt_l_d(f22, f24), "4620c5a5 cvt.l.d f22, f24"); in TEST()
1065 COMPARE(cvt_s_l(f22, f24), "46a0c5a0 cvt.s.l f22, f24"); in TEST()
1066 COMPARE(cvt_l_s(f22, f24), "4600c5a5 cvt.l.s f22, f24"); in TEST()
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll26 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
57 ; O32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
76 ; N32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
95 ; N64-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
/external/libjpeg-turbo/simd/
Djsimd_mips_dspr2_asm.h83 #define f24 $f24 macro

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