| /external/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 126 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; in isSI()
130 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; in isCI()
134 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; in isVI()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 37 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
69 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
81 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMStoreDeprecationInfo()
98 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMLoadDeprecationInfo()
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| D | ARMAsmBackend.h | 37 bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; } in hasNOP()
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| D | ARMAsmBackend.cpp | 161 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
549 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { in adjustFixupValue()
566 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { in adjustFixupValue()
576 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { in adjustFixupValue()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 359 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch()
364 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in selectArch()
368 if (!(getSTI().getFeatureBits()[Feature])) { in setFeatureBits()
372 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in setFeatureBits()
377 if (getSTI().getFeatureBits()[Feature]) { in clearFeatureBits()
381 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in clearFeatureBits()
387 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); in setModuleFeatureBits()
392 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); in clearModuleFeatureBits()
413 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); in MipsAsmParser()
417 llvm::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits())); in MipsAsmParser()
[all …]
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) { in encodeInstruction()
134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) && in encodeInstruction()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 736 (STI.getFeatureBits()[AArch64::HasV8_2aOps])) in printSysAlias()
788 if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) { in printSysAlias()
1140 AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid); in printPrefetchOp()
1153 AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid); in printPSBHintOp()
1354 Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(), in printBarrierOption()
1357 Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(), in printBarrierOption()
1371 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); in printMRSSystemRegister()
1382 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); in printMSRSystemRegister()
1394 AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid); in printSystemPStateField()
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| /external/llvm/lib/MC/ |
| D | MCInstrDesc.cpp | 26 if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) { in getDeprecatedInfo()
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| D | MCSubtargetInfo.cpp | 24 return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures); in getFeatures()
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| D | SubtargetFeature.cpp | 233 SubtargetFeatures::getFeatureBits(StringRef CPU, in getFeatureBits() function in SubtargetFeatures
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| /external/llvm/include/llvm/MC/ |
| D | SubtargetFeature.h | 111 FeatureBitset getFeatureBits(StringRef CPU,
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| D | MCSubtargetInfo.h | 71 const FeatureBitset& getFeatureBits() const { in getFeatureBits() function
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | AMDGPUMCTargetDesc.cpp | 76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.cpp | 126 return AMDGPU::getIsaVersion(getFeatureBits()); in getIsaVersion()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 259 return STI->getFeatureBits()[X86::Mode64Bit]; in is64BitMode()
262 return STI->getFeatureBits()[X86::Mode32Bit]; in is32BitMode()
265 return STI->getFeatureBits()[X86::Mode16Bit]; in is16BitMode()
1072 if (STI->getFeatureBits()[X86::Mode32Bit] != 0) in CreateX86AsmInstrumentation()
1074 if (STI->getFeatureBits()[X86::Mode64Bit] != 0) in CreateX86AsmInstrumentation()
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| D | X86AsmParser.cpp | 764 return getSTI().getFeatureBits()[X86::Mode64Bit]; in is64BitMode()
768 return getSTI().getFeatureBits()[X86::Mode32Bit]; in is32BitMode()
772 return getSTI().getFeatureBits()[X86::Mode16Bit]; in is16BitMode()
777 FeatureBitset OldMode = STI.getFeatureBits() & AllModes; in SwitchMode()
782 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes)); in SwitchMode()
810 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); in X86AsmParser()
1753 if (getSTI().getFeatureBits()[X86::FeatureAVX512] && in ParseIntelOperand()
1818 if (getSTI().getFeatureBits()[X86::FeatureAVX512]) in ParseATTOperand()
1828 if(getSTI().getFeatureBits()[X86::FeatureAVX512]) { in HandleAVX512Operand()
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| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| D | SparcInstPrinter.cpp | 38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; in isV9()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 252 const FeatureBitset &Bits = getFeatureBits(); in initSubtargetFeatures()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCTargetDesc.cpp | 123 auto Bits = STI.getFeatureBits(); in HexagonTargetELFStreamer()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 60 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), in MipsDisassembler()
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } in hasMips3()
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } in hasMips32()
45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in hasMips32r6()
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } in isGP64()
50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } in hasCnMips()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 127 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); in AArch64AsmParser()
2093 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid); in tryParsePrefetch()
2107 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); in tryParsePrefetch()
2133 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); in tryParsePSBHint()
2543 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) { in parseSysAlias()
2590 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) { in parseSysAlias()
2597 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) { in parseSysAlias()
2768 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid); in tryParseBarrierOperand()
2782 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); in tryParseBarrierOperand()
2812 getSTI().getFeatureBits(), IsKnown); in tryParseSysReg()
[all …]
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 390 if (getSTI().getFeatureBits().none()) { in AMDGPUAsmParser()
395 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); in AMDGPUAsmParser()
717 AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(getSTI().getFeatureBits()); in ParseDirectiveHSACodeObjectISA()
929 AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits()); in ParseDirectiveAMDKernelCodeT()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 438 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
695 assert(STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
971 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecoderGPRRegisterClass()
1015 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeDPRRegisterClass()
1363 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeCopMemInstruction()
2140 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction()
3310 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeT2LoadShift()
3397 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeT2LoadImm8()
3478 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeT2LoadImm12()
3596 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); in DecodeT2LoadLabel()
[all …]
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 96 if (STI.getFeatureBits()[ARM::HasV8Ops]) { in printInst()
305 STI.getFeatureBits()[ARM::FeatureVirtualization]) { in printInst()
700 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]); in printMemBOption()
800 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand()
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