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Searched refs:getOperand (Results 1 – 25 of 609) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp40 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
221 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
226 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) in EmitAnyX86InstComments()
228 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments()
230 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
231 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
237 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
242 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) in EmitAnyX86InstComments()
244 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments()
246 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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/external/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp76 return MI->getOperand( in getCFAluSize()
82 return MI->getOperand( in isCFAluEnabled()
99 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
124 if (LatrCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible()
125 RootCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible()
126 (LatrCFAlu->getOperand(KBank0Idx).getImm() != in mergeIfPossible()
127 RootCFAlu->getOperand(KBank0Idx).getImm() || in mergeIfPossible()
128 LatrCFAlu->getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
129 RootCFAlu->getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
140 if (LatrCFAlu->getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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DR600ISelLowering.cpp215 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) || in EmitInstrWithCustomInserter()
222 NewMI.addOperand(MI->getOperand(i)); in EmitInstrWithCustomInserter()
231 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
232 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
240 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
241 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
249 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
250 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
256 unsigned maskedRegister = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter()
264 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
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/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp105 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
123 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
125 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
131 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
157 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
174 if (LIS->getInterval(MI->getOperand(2).getReg()) in processBlock()
178 } else if (LIS->getInterval(MI->getOperand(3).getReg()) in processBlock()
200 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg(); in processBlock()
201 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg(); in processBlock()
203 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); in processBlock()
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DPPCISelDAGToDAG.cpp460 && isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
487 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) in isRotateAndMask()
520 SDValue Op0 = N->getOperand(0); in SelectBitfieldInsert()
521 SDValue Op1 = N->getOperand(1); in SelectBitfieldInsert()
541 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
542 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
543 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
544 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
551 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
552 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
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DPPCMIPeephole.cpp109 int Immed = MI.getOperand(3).getImm(); in simplifyCode()
119 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg()); in simplifyCode()
120 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg()); in simplifyCode()
129 unsigned FeedImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
131 = lookThruCopyLike(DefMI->getOperand(1).getReg()); in simplifyCode()
133 = lookThruCopyLike(DefMI->getOperand(2).getReg()); in simplifyCode()
141 TII->get(PPC::COPY), MI.getOperand(0).getReg()) in simplifyCode()
142 .addOperand(MI.getOperand(1)); in simplifyCode()
154 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
155 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp515 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in SelectIntrinsicChain()
583 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in SelectIntrinsicNoChain()
594 SDValue Wrapper = N->getOperand(1); in SelectTexSurfHandle()
595 SDValue GlobalVal = Wrapper.getOperand(0); in SelectTexSurfHandle()
601 SDValue Src = N->getOperand(0); in SelectAddrSpaceCast()
719 SDValue Chain = N->getOperand(0); in SelectLoad()
720 SDValue N1 = N->getOperand(1); in SelectLoad()
899 SDValue Chain = N->getOperand(0); in SelectLoadVector()
900 SDValue Op1 = N->getOperand(1); in SelectLoadVector()
941 N->getOperand(N->getNumOperands() - 1))->getZExtValue(); in SelectLoadVector()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp79 switch (MI->getOperand(0).getImm()) { in printInst()
115 const MCOperand &Dst = MI->getOperand(0); in printInst()
116 const MCOperand &MO1 = MI->getOperand(1); in printInst()
117 const MCOperand &MO2 = MI->getOperand(2); in printInst()
118 const MCOperand &MO3 = MI->getOperand(3); in printInst()
138 const MCOperand &Dst = MI->getOperand(0); in printInst()
139 const MCOperand &MO1 = MI->getOperand(1); in printInst()
140 const MCOperand &MO2 = MI->getOperand(2); in printInst()
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
179 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp100 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
102 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
114 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
115 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
126 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
127 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
136 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
145 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
146 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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DHexagonMCDuplexInfo.cpp192 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
193 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
210 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
211 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
231 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
232 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
57 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
95 assert(InstIn.getOperand(2).isImm()); in LowerDextDins()
96 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDextDins()
97 assert(InstIn.getOperand(3).isImm()); in LowerDextDins()
98 int64_t size = InstIn.getOperand(3).getImm(); in LowerDextDins()
104 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
110 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()
225 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
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/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp98 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
99 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
129 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
164 N->getOperand(2) }; in Select()
169 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
170 N->getOperand(2) }; in Select()
175 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
176 N->getOperand(2), N->getOperand(3) }; in Select()
181 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
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/external/llvm/unittests/IR/
DMDBuilderTest.cpp39 Metadata *Op = MD1->getOperand(0); in TEST_F()
53 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(0))); in TEST_F()
54 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(1))); in TEST_F()
55 ConstantInt *C0 = mdconst::extract<ConstantInt>(R1->getOperand(0)); in TEST_F()
56 ConstantInt *C1 = mdconst::extract<ConstantInt>(R1->getOperand(1)); in TEST_F()
67 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
68 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F()
69 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == nullptr); in TEST_F()
70 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == nullptr); in TEST_F()
78 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
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/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp66 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
67 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
77 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
78 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
89 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
90 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
99 int64_t RegIndex = MI->getOperand(1).getImm(); in EmitInstrWithCustomInserter()
102 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
109 unsigned maskedRegister = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter()
135 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
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DSIISelLowering.cpp83 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
84 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
87 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
88 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
98 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
99 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
102 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
103 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
113 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter()
114 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
400 SDValue MultHi = ADDENode->getOperand(0); in selectMADD()
401 SDValue MultLo = ADDCNode->getOperand(0); in selectMADD()
432 ADDCNode->getOperand(1), in selectMADD()
433 ADDENode->getOperand(1)); in selectMADD()
439 MultNode->getOperand(0),// Factor 0 in selectMADD()
440 MultNode->getOperand(1),// Factor 1 in selectMADD()
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
472 SDValue MultHi = SUBENode->getOperand(1); in selectMSUB()
473 SDValue MultLo = SUBCNode->getOperand(1); in selectMSUB()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp47 isa<ConstantInt>(I->getOperand(2))) in cheapToScalarize()
53 (cheapToScalarize(BO->getOperand(0), isConstant) || in cheapToScalarize()
54 cheapToScalarize(BO->getOperand(1), isConstant))) in cheapToScalarize()
58 (cheapToScalarize(CI->getOperand(0), isConstant) || in cheapToScalarize()
59 cheapToScalarize(CI->getOperand(1), isConstant))) in cheapToScalarize()
103 unsigned opId = (B0->getOperand(0) == PN) ? 1 : 0; in scalarizePHI()
105 ExtractElementInst::Create(B0->getOperand(opId), Elt, in scalarizePHI()
106 B0->getOperand(opId)->getName() + ".Elt"), in scalarizePHI()
138 if (Constant *C = dyn_cast<Constant>(EI.getOperand(0))) in visitExtractElementInst()
144 if (ConstantInt *IdxC = dyn_cast<ConstantInt>(EI.getOperand(1))) { in visitExtractElementInst()
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DInstCombineShifts.cpp25 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
94 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
97 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
114 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC, I) && in CanEvaluateShifted()
115 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC, I); in CanEvaluateShifted()
119 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
134 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
144 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
159 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp182 const MachineOperand &MO = MI->getOperand(i); in parseOperands()
242 if (MI->getOperand(2).isFI() && in isLoadFromStackSlot()
243 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { in isLoadFromStackSlot()
244 FrameIndex = MI->getOperand(2).getIndex(); in isLoadFromStackSlot()
245 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
266 if (MI->getOperand(2).isFI() && in isStoreToStackSlot()
267 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { in isStoreToStackSlot()
268 FrameIndex = MI->getOperand(0).getIndex(); in isStoreToStackSlot()
269 return MI->getOperand(2).getReg(); in isStoreToStackSlot()
336 I->getOperand(0).isMBB(); in AnalyzeBranch()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp597 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
601 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
615 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
619 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
625 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, in isNegatibleForFree()
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
656 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, in GetNegatedExpression()
659 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
661 Op.getOperand(1), Flags); in GetNegatedExpression()
664 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp38 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
39 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
42 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
43 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
44 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
51 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
58 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
59 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
69 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
70 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo()
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp4630 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
5967 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
5981 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
6060 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
6076 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
6086 const unsigned RtReg = Inst.getOperand(0).getReg(); in validateInstruction()
6100 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6106 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateInstruction()
6121 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
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/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp112 const MachineOperand &Src = MI->getOperand(1); in postRAConvertToLEA()
113 const MachineOperand &Dest = MI->getOperand(0); in postRAConvertToLEA()
138 if (!MI->getOperand(2).isImm()) { in postRAConvertToLEA()
146 if (MI->getOperand(1).getReg() != MI->getOperand(2).getReg()) { in postRAConvertToLEA()
184 MachineOperand &opnd = MI->getOperand(i); in usesRegister()
245 unsigned SrcReg = LEA->getOperand(1 + X86::AddrBaseReg).getReg(); in isLEASimpleIncOrDec()
246 unsigned DstReg = LEA->getOperand(0).getReg(); in isLEASimpleIncOrDec()
249 LEA->getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isLEASimpleIncOrDec()
250 LEA->getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && in isLEASimpleIncOrDec()
251 LEA->getOperand(AddrDispOp).isImm() && in isLEASimpleIncOrDec()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
83 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
93 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
94 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
116 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
159 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
255 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
262 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand()
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