| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGPrinter.cpp | 71 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget()
138 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
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| D | InstrEmitter.cpp | 115 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
125 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
127 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg()
198 User->getOperand(2).getResNo() == ResNo) { in getDstOfOnlyCopyToRegUse()
247 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters()
288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR()
672 SDValue Op = SDValue(Node, SD->getResNo()); in EmitDbgValue()
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| D | SDNodeDbgValue.h | 94 unsigned getResNo() const { assert (kind==SDNODE); return u.s.ResNo; } in getResNo() function
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| D | ResourcePriorityQueue.cpp | 134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta()
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
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| D | ScheduleDAGSDNodes.cpp | 121 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency()
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
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| D | SelectionDAG.cpp | 366 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
376 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
2156 if (Op.getResNo() != 1) in computeKnownBits()
2282 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
2617 if (Op.getResNo() != 1) in ComputeNumSignBits()
2724 if (Op.getResNo() == 0) { in ComputeNumSignBits()
6306 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && in ReplaceAllUsesWith()
6390 setRoot(SDValue(To, getRoot().getResNo())); in ReplaceAllUsesWith()
6418 const SDValue &ToOp = To[Use.getResNo()]; in ReplaceAllUsesWith()
6430 setRoot(SDValue(To[getRoot().getResNo()])); in ReplaceAllUsesWith()
[all …]
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| D | SelectionDAGBuilder.cpp | 734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), in getCopyToRegs()
957 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(), in resolveDanglingDebugInfo()
1340 SDValue(RetOp.getNode(), RetOp.getResNo() + i), in visitRet()
1378 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet()
2531 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); in visitSelect()
2532 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); in visitSelect()
2534 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i), in visitSelect()
2919 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
2925 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); in visitInsertValue()
2930 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
[all …]
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| D | LegalizeVectorOps.cpp | 182 return Result.getValue(Op.getResNo()); in TranslateLegalizeResults()
642 return (Op.getResNo() ? NewChain : Value); in ExpandLoad()
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| D | SelectionDAGDumper.cpp | 627 if (unsigned RN = Value.getResNo()) in printOperand()
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| D | ScheduleDAGFast.cpp | 231 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| D | LegalizeTypes.cpp | 91 if (UI.getUse().getResNo() == i) in PerformExpensiveChecks()
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| D | ScheduleDAGRRList.cpp | 964 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| D | SelectionDAGISel.cpp | 1829 if (Use.getResNo() == FlagResNo) in findGlueUse()
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| D | DAGCombiner.cpp | 5794 if (UI.getUse().getResNo() != N0.getResNo()) in ExtendUsesToFormExtLoad()
5829 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
7212 return Elt.getOperand(Elt.getResNo()).getNode(); in getBuildPairElt()
10524 if (UI.getUse().getResNo() != 0) in SliceUpLoad()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcher.cpp | 393 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl()
396 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
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| D | DAGISelMatcherOpt.cpp | 53 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes()
436 CTM->getResNo() != 0 || in FactorNodes()
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| D | DAGISelMatcherEmitter.cpp | 381 assert(cast<CheckTypeMatcher>(N)->getResNo() == 0 && in EmitMatcher()
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| D | DAGISelMatcher.h | 538 unsigned getResNo() const { return ResNo; } in getResNo() function
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 111 unsigned getResNo() const { return ResNo; }
201 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
261 unsigned getResNo() const { return Val.getResNo(); }
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1237 if (N.getResNo() != 0) break; in matchAddressRecursively()
2028 if (FlagUI.getUse().getResNo() != 1) continue; in hasNoSignedComparisonUses()
2083 if (StoredVal.getResNo() != 0) return false; in isLoadIncOrDecStore()
2137 if (UI.getUse().getResNo() != 0) in isLoadIncOrDecStore()
2796 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) && in Select()
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| D | X86ISelLowering.cpp | 13803 if (Op.getResNo() != 0 || NeedOF || NeedCF) { in EmitTest()
14776 if (Op.getResNo() == 1 && in isX86LogicalCmp()
14790 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) in isX86LogicalCmp()
15469 Cond.getOperand(0).getResNo() == 1 && in LowerBRCOND()
22548 if (Op.getResNo() == 0) in computeKnownBitsForTargetNode()
23823 if (UI.getUse().getResNo() != InputVector.getResNo()) in PerformEXTRACT_VECTOR_ELTCombine()
24581 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0) in checkBoolTestSetCCCombine()
27021 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 && in PerformSExtCombine()
27192 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 && in PerformZExtCombine()
27344 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo()); in PerformSETCCCombine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) in selectMADD()
487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) in selectMSUB()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3602 if (LHS.getResNo() == 1 && isOneConstant(RHS) && in LowerBR_CC()
4051 if (CCVal.getResNo() == 1 && in LowerSELECT()
8685 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result. in performPostLD1Combine()
8698 || UI.getUse().getResNo() != Addr.getResNo()) in performPostLD1Combine()
9065 UI.getUse().getResNo() != Addr.getResNo()) in performNEONPostLDSTCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3457 if (Cond.getResNo() == 1 && in LowerSELECT()
9255 Op0.getResNo() == 0 && Op1.getResNo() == 1) in PerformVMOVDRRCombine()
9502 UI.getUse().getResNo() != Addr.getResNo()) in CombineBaseUpdate()
9737 if (UI.getUse().getResNo() == NumVecs) in CombineVLDDUP()
9761 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP()
11176 if (Op.getResNo() == 0) in computeKnownBitsForTargetNode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1864 if (Op.getResNo() == 1) { in computeKnownBitsForTargetNode()
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