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Searched refs:hasVSX (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp217 return ST->hasVSX() ? 64 : 32; in getNumberOfRegisters()
300 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { in getVectorInstrCost()
350 bool IsVSXType = ST->hasVSX() && in getMemoryOpCost()
371 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) in getMemoryOpCost()
DPPCCallingConv.td68 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
121 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
183 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
DPPCVSXCopy.cpp161 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCSubtarget.h229 bool hasVSX() const { return HasVSX; } in hasVSX() function
DPPCVSXFMAMutate.cpp329 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCRegisterInfo.cpp105 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
136 if (Subtarget.hasVSX()) in getCallPreservedMask()
294 if (Subtarget.hasVSX()) { in getLargestLegalSuperClass()
DPPCISelDAGToDAG.cpp2087 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; in SelectCC()
2361 PPCSubTarget->hasVSX(), Swap, Negate); in SelectSETCC()
2368 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : in SelectSETCC()
2810 if (PPCSubTarget->hasVSX()) in Select()
2831 if (PPCSubTarget->hasVSX()) { in Select()
2838 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || in Select()
DPPCVSXSwapRemoval.cpp198 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCISelLowering.cpp526 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) { in PPCTargetLowering()
553 if (Subtarget.hasVSX()) { in PPCTargetLowering()
2867 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
3299 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
7409 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
9163 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
9185 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
10260 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10274 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10486 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) { in PerformDAGCombine()
[all …]
DPPCInstrVSX.td86 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;