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Searched refs:i5 (Results 1 – 25 of 148) sorted by relevance

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/external/valgrind/none/tests/s390x/
Drxsbg.c4 #define DO_RXSBG(insn, _r1, _r2, i3, i4, i5) \ argument
9 asm volatile( insn(1,2, i3, i4, i5) \
15 …printf(#insn " r1(==%16.16lX),r2(==%16.16lX),0x" #i3 ",0x" #i4 ",0x" #i5 " = %16.16lX (cc=%d)\n", …
18 #define r1sweep(i, r2, i3, i4, i5) \ argument
20 DO_RXSBG(i, 000000000000000000ul, r2, i3, i4, i5); \
21 DO_RXSBG(i, 0x0000ffffccccaaaaul, r2, i3, i4, i5); \
22 DO_RXSBG(i, 0xfffffffffffffffful, r2, i3, i4, i5); \
25 #define r2sweep(i, i3, i4, i5) \ argument
27 r1sweep(i, 0x0000000000000000ul, i3, i4, i5); \
28 r1sweep(i, 0x5555ccccffff0000ul, i3, i4, i5); \
[all …]
/external/v8/test/mjsunit/asm/embenchen/
Dlua_binarytrees.js7386 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
7400 i5 = i6 << 1;
7401 i3 = 12952 + (i5 << 2) | 0;
7402 i5 = 12952 + (i5 + 2 << 2) | 0;
7403 i7 = HEAP32[i5 >> 2] | 0;
7414 HEAP32[i5 >> 2] = i4;
7440 i5 = i7 >>> 2 & 4;
7441 i7 = i7 >>> i5;
7445 i3 = (i6 | i2 | i5 | i4 | i3) + (i7 >>> i3) | 0;
7449 i5 = HEAP32[i7 >> 2] | 0;
[all …]
Dbox2d.js6152 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
6166 i5 = i6 << 1;
6167 i3 = 7200 + (i5 << 2) | 0;
6168 i5 = 7200 + (i5 + 2 << 2) | 0;
6169 i7 = HEAP32[i5 >> 2] | 0;
6180 HEAP32[i5 >> 2] = i4;
6206 i5 = i7 >>> 2 & 4;
6207 i7 = i7 >>> i5;
6211 i3 = (i6 | i2 | i5 | i4 | i3) + (i7 >>> i3) | 0;
6215 i5 = HEAP32[i7 >> 2] | 0;
[all …]
Dzlib.js5772 …var i1 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i12 = 0, i13 = 0, i1…
5810 i5 = HEAP32[i16 >> 2] | 0;
5854 i65 = i5;
7479 HEAP32[i71 >> 2] = i5 - i16 + (HEAP32[i71 >> 2] | 0);
7501 i72 = ((i5 | 0) == (i16 | 0) & i13 | (i3 | 0) == 4) & (i61 | 0) == 0 ? -5 : i61;
7507 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
7521 i5 = i6 << 1;
7522 i3 = 14512 + (i5 << 2) | 0;
7523 i5 = 14512 + (i5 + 2 << 2) | 0;
7524 i7 = HEAP32[i5 >> 2] | 0;
[all …]
Dfannkuch.js5744 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
5758 i5 = i6 << 1;
5759 i3 = 96 + (i5 << 2) | 0;
5760 i5 = 96 + (i5 + 2 << 2) | 0;
5761 i7 = HEAP32[i5 >> 2] | 0;
5772 HEAP32[i5 >> 2] = i4;
5798 i5 = i7 >>> 2 & 4;
5799 i7 = i7 >>> i5;
5803 i3 = (i6 | i2 | i5 | i4 | i3) + (i7 >>> i3) | 0;
5807 i5 = HEAP32[i7 >> 2] | 0;
[all …]
Dfasta.js5920 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
5934 i5 = i6 << 1;
5935 i3 = 624 + (i5 << 2) | 0;
5936 i5 = 624 + (i5 + 2 << 2) | 0;
5937 i7 = HEAP32[i5 >> 2] | 0;
5948 HEAP32[i5 >> 2] = i4;
5974 i5 = i7 >>> 2 & 4;
5975 i7 = i7 >>> i5;
5979 i3 = (i6 | i2 | i5 | i4 | i3) + (i7 >>> i3) | 0;
5983 i5 = HEAP32[i7 >> 2] | 0;
[all …]
Dmemops.js5689 …var i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 …
5703 i5 = i6 << 1;
5704 i3 = 80 + (i5 << 2) | 0;
5705 i5 = 80 + (i5 + 2 << 2) | 0;
5706 i7 = HEAP32[i5 >> 2] | 0;
5717 HEAP32[i5 >> 2] = i4;
5743 i5 = i7 >>> 2 & 4;
5744 i7 = i7 >>> i5;
5748 i3 = (i6 | i2 | i5 | i4 | i3) + (i7 >>> i3) | 0;
5752 i5 = HEAP32[i7 >> 2] | 0;
[all …]
/external/llvm/test/MC/Sparc/
Dsparcv9-instructions.s100 ! V8-NEXT: ldx [%g2 + %i5],%fsr
101 ! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
102 ldx [%g2 + %i5],%fsr
110 ! V8-NEXT: stx %fsr,[%g2 + %i5]
111 ! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
112 stx %fsr,[%g2 + %i5]
237 ! V8-NEXT: rdpr %tpc,%i5
238 ! V9: rdpr %tpc, %i5 ! encoding: [0xbb,0x50,0x00,0x00]
239 rdpr %tpc,%i5
241 ! V8-NEXT: rdpr %tnpc,%i5
[all …]
Dsparc-nop-data.s8 xor %i5, %i5, %i5
10 xor %i5, %i5, %i5
Dsparc-special-registers.s46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/external/v8/test/mjsunit/compiler/
Dregress-177883.js68 …var i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i12 = 0, i13 = 0, i1…
72 i5 = i4 | 0;
73 HEAPF32[i5 >> 2] = 0.0;
93 HEAPF32[i5 >> 2] = +HEAPF32[i9 >> 2];
98 HEAPF32[i5 >> 2] = +HEAPF32[i13 >> 2];
105 HEAPF32[i5 >> 2] = +HEAPF32[i9 >> 2];
112 HEAPF32[i5 >> 2] = +HEAPF32[i9 >> 2];
119 HEAPF32[i5 >> 2] = +HEAPF32[i13 >> 2];
124 HEAPF32[i5 >> 2] = +HEAPF32[i9 >> 2];
131 HEAPF32[i5 >> 2] = +HEAPF32[i13 >> 2];
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Dloop_evaluate_5.ll7 define i32 @testcase(i5 zeroext %k) nounwind readnone {
16 %k_01 = phi i5 [ %indvar_next1, %bb2 ], [ 0, %bb.nph ] ; <i5> [#uses=2]
17 %tmp2 = zext i5 %k_01 to i32 ; <i32> [#uses=1]
19 %indvar_next1 = add i5 %k_01, 1 ; <i5> [#uses=2]
23 %phitmp = icmp eq i5 %indvar_next1, -16 ; <i1> [#uses=1]
DiterationCount_zext_or_trunc.ll7 define i32 @testcase(i5 zeroext %k) {
13 %indvar_next1 = add i5 %k_0, 1 ; <i5> [#uses=1]
17 %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; <i5> [#uses=2]
19 %tmp2 = zext i5 %k_0 to i32 ; <i32> [#uses=1]
/external/libcxx/test/std/iterators/stream.iterators/istream.iterator/istream.iterator.ops/
Dequal.pass.cpp34 std::istream_iterator<int> i5; in main() local
39 assert(i1 != i5); in main()
44 assert(i2 != i5); in main()
48 assert(i3 != i5); in main()
51 assert(i4 == i5); in main()
/external/clang/test/CodeGen/
Darm64-arguments.c297 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
350 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
405 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
460 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
517 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/mesa3d/src/mesa/sparc/
Dsparc_clip.S80 LDPTR [%i1 + V4F_START], %i5
132 st %g0, [%i5 + 0x00] ! LSU
135 st %g0, [%i5 + 0x04] ! LSU
137 st %g0, [%i5 + 0x08] ! LSU
139 st %f4, [%i5 + 0x0c] ! LSU Group
144 st %f0, [%i5 + 0x00] ! LSU Group
146 st %f1, [%i5 + 0x04] ! LSU Group
148 st %f2, [%i5 + 0x08] ! LSU Group
149 st %f8, [%i5 + 0x0c] ! LSU Group
150 3: add %i5, 0x10, %i5 ! IEU1
/external/llvm/test/CodeGen/X86/
Dcode_placement_eh.ll14 br i1 undef, label %bb18.i5.i, label %bb15
16 .noexc6.i.i: ; preds = %bb18.i5.i
18 to label %bb18.i5.i unwind label %lpad.i.i ; <float> [#uses=0]
20 bb18.i5.i: ; preds = %.noexc6.i.i, %bb51.i
24 lpad.i.i: ; preds = %bb18.i5.i, %.noexc6.i.i
D2009-01-18-ConstantExprCrash.ll29 br label %bb4.i5.i141
31 bb4.i5.i141: ; preds = %bb4.i5.i141, %_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73
32 br label %bb4.i5.i141
D2007-11-30-LoadFolding-Bug.ll9 br label %bb.i5
11 bb.i5: ; preds = %bb.i5, %entry
12 %nfft_init.0.i = phi i32 [ 1, %entry ], [ %tmp7.i3, %bb.i5 ] ; <i32> [#uses=1]
13 %foo = phi i1 [1, %entry], [0, %bb.i5]
15 br i1 %foo, label %bb.i5, label %mp_unexp_mp2d.exit.i
17 mp_unexp_mp2d.exit.i: ; preds = %bb.i5
Demutls.ll38 @i5 = external hidden thread_local global i32
151 ; X32: movl $__emutls_v.i5, (%esp)
158 %tmp1 = load i32, i32* @i5
164 ; X32: movl $__emutls_v.i5, (%esp)
170 ret i32* @i5
264 ; X32-NOT: __emutls_v.i5:
265 ; X32 .hidden __emutls_v.i5
266 ; X32-NOT: __emutls_v.i5:
325 ; X64-NOT: __emutls_v.i5:
326 ; X64 .hidden __emutls_v.i5
[all …]
/external/llvm/test/CodeGen/SPARC/
D64spill.ll13 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
24 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
35 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
47 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
58 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
69 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
80 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
91 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
102 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
113 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
/external/llvm/test/CodeGen/PowerPC/
Dcr-spills.ll80 %cond.i5.i1516 = select i1 %cmp.i4.i1515, i32 %cond.i.i1514, i32 %1
83 %sub301 = sub nsw i32 %cond.i5.i1516, %conv300
99 %cond.i5.i1508 = select i1 %cmp.i4.i1507, i32 %cond.i.i1506, i32 %1
100 %sub329 = sub nsw i32 %cond.i5.i1508, 0
108 %cond.i5.i1504 = select i1 %cmp.i4.i1503, i32 %cond.i.i1502, i32 %1
112 %sub343 = sub nsw i32 %cond.i5.i1504, %conv342
127 %cond.i5.i1500 = select i1 %cmp.i4.i1499, i32 %cond.i.i1498, i32 %1
131 %sub357 = sub nsw i32 %cond.i5.i1500, %conv356
146 %cond.i5.i1496 = select i1 %cmp.i4.i1495, i32 %cond.i.i1494, i32 %1
150 %sub371 = sub nsw i32 %cond.i5.i1496, %conv370
[all …]
/external/lzma/CPP/Common/
DMyCom.h212 #define MY_UNKNOWN_IMP5(i1, i2, i3, i4, i5) MY_UNKNOWN_IMP_SPEC( \ argument
218 MY_QUERYINTERFACE_ENTRY(i5) \
221 #define MY_UNKNOWN_IMP6(i1, i2, i3, i4, i5, i6) MY_UNKNOWN_IMP_SPEC( \ argument
227 MY_QUERYINTERFACE_ENTRY(i5) \
231 #define MY_UNKNOWN_IMP7(i1, i2, i3, i4, i5, i6, i7) MY_UNKNOWN_IMP_SPEC( \ argument
237 MY_QUERYINTERFACE_ENTRY(i5) \
/external/llvm/test/Assembler/
Duselistorder.ll10 @glob1 = global i5 7
11 @glob2 = global i5 7
12 @glob3 = global i5 7
55 uselistorder i5 7, { 1, 0, 2 }
/external/libchrome/sandbox/linux/bpf_dsl/
Dcodegen_unittest.cc266 CodeGen::Node i5 = MakeInstruction(BPF_JMP + BPF_JEQ + BPF_K, 1, i6, i7); in TEST_F() local
267 CodeGen::Node i4 = MakeInstruction(BPF_LD + BPF_W + BPF_ABS, 0, i5); in TEST_F()
268 CodeGen::Node i3 = MakeInstruction(BPF_JMP + BPF_JEQ + BPF_K, 2, i4, i5); in TEST_F()
288 CodeGen::Node i5 = MakeInstruction(BPF_RET + BPF_K, 1); in TEST_F() local
289 CodeGen::Node i4 = MakeInstruction(BPF_LD + BPF_W + BPF_ABS, 0, i5); in TEST_F()
290 CodeGen::Node i3 = MakeInstruction(BPF_JMP + BPF_JEQ + BPF_K, 2, i4, i5); in TEST_F()
316 CodeGen::Node i5 = MakeInstruction(BPF_JMP + BPF_JEQ + BPF_K, 1, i6, i7); in TEST_F() local
318 CodeGen::Node i3 = MakeInstruction(BPF_JMP + BPF_JEQ + BPF_K, 2, i4, i5); in TEST_F()

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