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Searched refs:imm19 (Results 1 – 20 of 20) sorted by relevance

/external/v8/src/arm64/
Dassembler-arm64-inl.h1014 Instr Assembler::ImmCondBranch(int imm19) {
1015 CHECK(is_int19(imm19));
1016 return truncate_to_int19(imm19) << ImmCondBranch_offset;
1020 Instr Assembler::ImmCmpBranch(int imm19) {
1021 CHECK(is_int19(imm19));
1022 return truncate_to_int19(imm19) << ImmCmpBranch_offset;
1094 Instr Assembler::ImmLLiteral(int imm19) {
1095 CHECK(is_int19(imm19));
1096 return truncate_to_int19(imm19) << ImmLLiteral_offset;
Dassembler-arm64.h981 void b(int imm19, Condition cond);
989 void cbz(const Register& rt, int imm19);
993 void cbnz(const Register& rt, int imm19);
1389 void ldr_pcrel(const CPURegister& rt, int imm19);
1709 inline static Instr ImmCondBranch(int imm19);
1710 inline static Instr ImmCmpBranch(int imm19);
1721 inline static Instr ImmLLiteral(int imm19);
Dassembler-arm64.cc995 void Assembler::b(int imm19, Condition cond) { in b() argument
996 Emit(B_cond | ImmCondBranch(imm19) | cond); in b()
1019 int imm19) { in cbz() argument
1021 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); in cbz()
1033 int imm19) { in cbnz() argument
1035 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); in cbnz()
1676 void Assembler::ldr_pcrel(const CPURegister& rt, int imm19) { in ldr_pcrel() argument
1680 Emit(LoadLiteralOpFor(rt) | ImmLLiteral(imm19) | Rt(rt)); in ldr_pcrel()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td677 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
678 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
680 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
681 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
683 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
684 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
686 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
687 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
732 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
734 "fb$cond $cc, $imm19", []>;
[all …]
DSparcInstrFormats.td68 bits<19> imm19;
77 let Inst{18-0} = imm19;
DSparcInstr64Bit.td312 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
/external/vixl/src/vixl/a64/
Dassembler-a64.h1209 void b(int imm19, Condition cond);
1221 void cbz(const Register& rt, int imm19);
1227 void cbnz(const Register& rt, int imm19);
1837 void ldr(const CPURegister& rt, int imm19);
1840 void ldrsw(const Register& rt, int imm19);
1926 void prfm(PrefetchOperation op, int imm19);
3848 static Instr ImmCondBranch(int imm19) { in ImmCondBranch() argument
3849 VIXL_ASSERT(is_int19(imm19)); in ImmCondBranch()
3850 return truncate_to_int19(imm19) << ImmCondBranch_offset; in ImmCondBranch()
3853 static Instr ImmCmpBranch(int imm19) { in ImmCmpBranch() argument
[all …]
Dassembler-a64.cc593 ptrdiff_t imm19 = ldr->ImmLLiteral(); in place() local
594 VIXL_ASSERT(imm19 <= 0); in place()
595 done = (imm19 == 0); in place()
596 offset += imm19 * kLiteralEntrySize; in place()
669 void Assembler::b(int imm19, Condition cond) { in b() argument
670 Emit(B_cond | ImmCondBranch(imm19) | cond); in b()
701 int imm19) { in cbz() argument
702 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); in cbz()
715 int imm19) { in cbnz() argument
716 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); in cbnz()
[all …]
/external/v8/src/mips/
Ddisasm-mips.cc330 int32_t imm19 = instr->Imm19Value(); in PrintSImm19() local
332 imm19 <<= (32 - kImm19Bits); in PrintSImm19()
333 imm19 >>= (32 - kImm19Bits); in PrintSImm19()
334 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19); in PrintSImm19()
Dsimulator-mips.cc4299 int32_t imm19 = instr->Imm19Value(); in DecodeTypeImmediate() local
4305 imm19 <<= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4306 imm19 >>= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4307 addr = current_pc + (imm19 << 2); in DecodeTypeImmediate()
4313 int32_t se_imm19 = imm19 | ((imm19 & 0x40000) ? 0xfff80000 : 0); in DecodeTypeImmediate()
Dassembler-mips.cc1849 void Assembler::addiupc(Register rs, int32_t imm19) { in addiupc() argument
1851 DCHECK(rs.is_valid() && is_int19(imm19)); in addiupc()
1852 uint32_t imm21 = ADDIUPC << kImm19Bits | (imm19 & kImm19Mask); in addiupc()
Dassembler-mips.h775 void addiupc(Register rs, int32_t imm19);
/external/v8/src/mips64/
Ddisasm-mips64.cc333 int32_t imm19 = instr->Imm19Value(); in PrintSImm19() local
335 imm19 <<= (32 - kImm19Bits); in PrintSImm19()
336 imm19 >>= (32 - kImm19Bits); in PrintSImm19()
337 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19); in PrintSImm19()
Dsimulator-mips64.cc4538 int32_t imm19 = instr->Imm19Value(); in DecodeTypeImmediate() local
4553 imm19 <<= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4554 imm19 >>= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4555 addr = current_pc + (imm19 << 2); in DecodeTypeImmediate()
4562 imm19 <<= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4563 imm19 >>= (kOpcodeBits + kRsBits + 2); in DecodeTypeImmediate()
4564 addr = current_pc + (imm19 << 2); in DecodeTypeImmediate()
4571 imm19 | ((imm19 & 0x40000) ? 0xfffffffffff80000 : 0); in DecodeTypeImmediate()
Dassembler-mips64.cc2118 void Assembler::addiupc(Register rs, int32_t imm19) { in addiupc() argument
2120 DCHECK(rs.is_valid() && is_int19(imm19)); in addiupc()
2121 uint32_t imm21 = ADDIUPC << kImm19Bits | (imm19 & kImm19Mask); in addiupc()
Dassembler-mips64.h820 void addiupc(Register rs, int32_t imm19);
/external/vixl/doc/
Dsupported-instructions.md112 void b(int imm19, Condition cond)
223 void cbnz(const Register& rt, int imm19)
237 void cbz(const Register& rt, int imm19)
603 Load integer or FP register from pc + imm19 << 2.
605 void ldr(const CPURegister& rt, int imm19)
657 Load word with sign extension from pc + imm19 << 2.
659 void ldrsw(const Register& rt, int imm19)
912 Prefetch from pc + imm19 << 2.
914 void prfm(PrefetchOperation op, int imm19)
/external/v8/test/cctest/
Dtest-assembler-mips.cc5028 uint64_t run_addiupc(int32_t imm19) { in run_addiupc() argument
5034 __ addiupc(v0, imm19); in run_addiupc()
5047 CALL_GENERATED_CODE(isolate, f, imm19, 0, 0, 0, 0)); in run_addiupc()
5058 int32_t imm19; in TEST() member
5073 uint32_t res = run_addiupc(tc[i].imm19); in TEST()
5075 uint32_t expected_res = PC + (tc[i].imm19 << 2); in TEST()
Dtest-assembler-mips64.cc5400 uint64_t run_addiupc(int32_t imm19) { in run_addiupc() argument
5406 __ addiupc(v0, imm19); in run_addiupc()
5430 int32_t imm19; in TEST() member
5445 uint64_t res = run_addiupc(tc[i].imm19); in TEST()
5447 uint64_t expected_res = PC + (tc[i].imm19 << 2); in TEST()
/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c4924 UInt imm19 = INSN(23,5); in dis_ARM64_load_store() local
4927 ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); in dis_ARM64_load_store()
5630 UInt imm19 = INSN(23,5); in dis_ARM64_load_store() local
5632 ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); in dis_ARM64_load_store()