| /external/llvm/include/llvm/MC/ |
| D | MCInstrAnalysis.h | 46 virtual bool isIndirectBranch(const MCInst &Inst) const { in isIndirectBranch() function
47 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
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| D | MCInstrDesc.h | 237 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); } in isIndirectBranch() function
244 return isBranch() & !isBarrier() & !isIndirectBranch(); in isConditionalBranch()
252 return isBranch() & isBarrier() & !isIndirectBranch(); in isUnconditionalBranch()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIsetDx.td | 32 …GenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideE…
53 …dicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
122 …deGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideE…
211 …isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 …ated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideE…
560 …sCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
599 …ses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideE…
696 …redicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
706 …redicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
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| /external/llvm/lib/MC/ |
| D | MCInstrDesc.cpp | 35 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 440 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
449 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
457 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 124 if (J->isIndirectBranch()) { in processBlock()
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| D | PPCInstr64Bit.td | 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
271 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
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| /external/llvm/lib/Target/Mips/ |
| D | MipsLongBranch.cpp | 142 assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found."); in splitMBB()
184 if ((Br != End) && !Br->isIndirectBranch() && in initMBBInfo()
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| D | MipsInstrInfo.cpp | 201 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None; in AnalyzeBranch()
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| D | MicroMipsInstrInfo.td | 434 let isIndirectBranch = 1;
444 let isIndirectBranch = 1;
463 let isIndirectBranch = 1;
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| D | MipsInstrInfo.td | 999 let isIndirectBranch = 1;
1564 let isIndirectBranch = 1;
1730 let isIndirectBranch=1;
1738 let isIndirectBranch=1;
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| D | Mips16InstrInfo.td | 766 let isIndirectBranch = 1;
774 let isIndirectBranch = 1;
781 let isIndirectBranch = 1;
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| D | MicroMips32r6InstrInfo.td | 410 let isIndirectBranch = 1;
422 let isIndirectBranch = 1;
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| D | Mips32r6InstrInfo.td | 404 bit isIndirectBranch = 1;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 227 bool isIndirectBranch : 1; variable
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| D | InstrInfoEmitter.cpp | 483 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 302 isIndirectBranch = R->getValueAsBit("isIndirectBranch"); in CodeGenInstruction()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 677 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
958 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
963 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
968 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
973 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
1107 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 283 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() && in checkBranches()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 134 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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| /external/llvm/lib/CodeGen/ |
| D | TailDuplication.cpp | 578 HasIndirectbr = TailBB.back().isIndirectBranch(); in shouldTailDuplicate()
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| /external/llvm/docs/TableGen/ |
| D | index.rst | 109 bit isIndirectBranch = 0;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 433 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1488 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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| D | ARMInstrInfo.td | 2158 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2262 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2280 } // isNotDuplicable = 1, isIndirectBranch = 1
5350 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | AsmPrinter.cpp | 2510 if (!MI.isBranch() || MI.isIndirectBranch()) in isBlockOnlyReachableByFallthrough()
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