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/external/webrtc/webrtc/base/
Dbytebuffer_unittest.cc20 uint16_t n16 = 1; in TEST() local
24 EXPECT_EQ(n16, NetworkToHost16(HostToNetwork16(n16))); in TEST()
30 EXPECT_EQ(n16, HostToNetwork16(n16)); in TEST()
35 EXPECT_EQ(n16 >> 8, GetBE16(&n16)); in TEST()
40 EXPECT_NE(n16, HostToNetwork16(n16)); in TEST()
45 EXPECT_EQ(GetBE16(&n16), HostToNetwork16(n16)); in TEST()
50 EXPECT_EQ(n16 << 8, GetBE16(&n16)); in TEST()
/external/regex-re2/re2/
Dmake_unicode_groups.py27 n16 = 0 variable
70 global n16
72 n16 += len(range16)
101 print "// %d 16-bit ranges, %d 32-bit ranges" % (n16, n32)
/external/llvm/test/CodeGen/Hexagon/
Dusr-ovf-dep.ll2 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
11 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
Dstore-widen-negv2.ll6 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
Dsdr-basic.ll5 …2:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
Dstore-widen.ll2 …2:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
Dstore-widen-aliased-load.ll5 …2:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
Dexpand-condsets-undef.ll4 target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
/external/llvm/test/CodeGen/NVPTX/
Dmodule-inline-asm.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dvector-global.ll3 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
Dsext-params.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Drsqrt.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dload-sext-i1.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dbug22246.ll3 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
Di1-global.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dadd-128bit.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dldu-i8.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Di1-param.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dvec-param-load.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dfp-literals.ll4 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Di8-param.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dlower-alloca.ll4 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Dctpop.ll3 …16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
/external/llvm/test/Transforms/NaryReassociate/
Dnary-mul.ll3 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
/external/llvm/test/Analysis/Lint/
Daddress-spaces.ll3 target datalayout = "p32:32:32-p1:16:16:16-n16:32"

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