Searched refs:numOperands (Results 1 – 5 of 5) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUAsmPrinter.cpp | 68 unsigned numOperands = MI.getNumOperands(); in EmitProgramInfo() local
69 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { in EmitProgramInfo()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 270 unsigned numOperands = MI.getNumOperands(); in EmitProgramInfoR600() local
271 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { in EmitProgramInfoR600()
341 unsigned numOperands = MI.getNumOperands(); in getSIProgramInfo() local
342 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { in getSIProgramInfo()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 1923 SDValue *Operands, unsigned numOperands,
1929 InitOperands(Ops, Operands, numOperands);
2020 SDValue *Operands, unsigned numOperands, SDVTList VTs,
2023 InitOperands(Ops, Operands, numOperands);
2044 unsigned numOperands, SDVTList VTs, ISD::LoadExtType ETy,
2046 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, Operands, numOperands,
2066 unsigned numOperands, SDVTList VTs, bool isTrunc, EVT MemVT,
2068 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, Operands, numOperands,
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 519 unsigned numOperands = OperandList.size(); in emitInstructionSpecifier() local
525 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); in emitInstructionSpecifier()
527 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { in emitInstructionSpecifier()
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| /external/llvm/lib/IR/ |
| D | Core.cpp | 796 const unsigned numOperands = N->getNumOperands(); in LLVMGetMDNodeOperands() local
798 for (unsigned i = 0; i < numOperands; i++) in LLVMGetMDNodeOperands()
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