Home
last modified time | relevance | path

Searched refs:qb (Results 1 – 25 of 58) sorted by relevance

123

/external/llvm/test/MC/Mips/dspr2/
Dvalid.s6 …absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x7c,0x04,0…
18 …addu.qb $6, $7, $8 # CHECK: addu.qb $6, $7, $8 # encoding: [0x7c,0xe8,0…
19 …addu_s.qb $9, $10, $11 # CHECK: addu_s.qb $9, $10, $11 # encoding: [0x7d,0x4b,0…
21 …adduh.qb $15, $16, $17 # CHECK: adduh.qb $15, $16, $17 # encoding: [0x7e,0x11,0…
22 …adduh_r.qb $18, $19, $20 # CHECK: adduh_r.qb $18, $19, $20 # encoding: [0x7e,0x74,0…
30 …cmpgdu.eq.qb $2, $3, $4 # CHECK: cmpgdu.eq.qb $2, $3, $4 # encoding: [0x7c,0x64,0…
31 …cmpgdu.lt.qb $5, $6, $7 # CHECK: cmpgdu.lt.qb $5, $6, $7 # encoding: [0x7c,0xc7,0…
32 …cmpgdu.le.qb $8, $9, $10 # CHECK: cmpgdu.le.qb $8, $9, $10 # encoding: [0x7d,0x2a,0…
33 …cmpgu.eq.qb $11, $12, $13 # CHECK: cmpgu.eq.qb $11, $12, $13 # encoding: [0x7d,0x8d,0…
34 …cmpgu.lt.qb $14, $15, $16 # CHECK: cmpgu.lt.qb $14, $15, $16 # encoding: [0x7d,0xf0,0…
[all …]
Dinvalid.s15 shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
16 shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
17 shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
18 shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
/external/llvm/test/MC/Mips/micromips-dspr2/
Dvalid.s5 absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c]
12 addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
14 addu_s.qb $3, $4, $5 # CHECK: addu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0xcd]
15 adduh.qb $3, $4, $5 # CHECK: adduh.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x4d]
16 adduh_r.qb $3, $4, $5 # CHECK: adduh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x4d]
51 pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed]
62 …precr.qb.ph $1, $2, $3 # CHECK: precr.qb.ph $1, $2, $3 # encoding: [0x00,0x62,0x08,0…
66 …precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0…
67 …precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0…
73 shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
[all …]
Dinvalid.s4 shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
5 shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
6 shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
7 shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
/external/llvm/test/MC/Mips/dsp/
Dvalid.s11 …addu.qb $6, $7, $8 # CHECK: addu.qb $6, $7, $8 # encoding: [0x7c,0x…
12 …addu_s.qb $9, $10, $11 # CHECK: addu_s.qb $9, $10, $11 # encoding: [0x7d,0x…
19 …cmpgu.eq.qb $11, $12, $13 # CHECK: cmpgu.eq.qb $11, $12, $13 # encoding: [0x7d,0x…
20 …cmpgu.lt.qb $14, $15, $16 # CHECK: cmpgu.lt.qb $14, $15, $16 # encoding: [0x7d,0x…
21 …cmpgu.le.qb $17, $18, $19 # CHECK: cmpgu.le.qb $17, $18, $19 # encoding: [0x7e,0x…
22 …cmpu.eq.qb $20, $21 # CHECK: cmpu.eq.qb $20, $21 # encoding: [0x7e,0x…
23 …cmpu.lt.qb $22, $23 # CHECK: cmpu.lt.qb $22, $23 # encoding: [0x7e,0x…
24 …cmpu.le.qb $24, $25 # CHECK: cmpu.le.qb $24, $25 # encoding: [0x7f,0x…
83 …pick.qb $2, $4, $8 # CHECK: pick.qb $2, $4, $8 # encoding: [0x7c,0x…
95 …precrq.qb.ph $16, $17, $18 # CHECK: precrq.qb.ph $16, $17, $18 # encoding: [0x7e,0x…
[all …]
Dinvalid.s8 shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
9 shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
20 shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
21 shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
/external/llvm/test/MC/Mips/micromips-dsp/
Dvalid.s6 addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
7 addu_s.qb $3, $4, $5 # CHECK: addu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0xcd]
38 pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed]
50 …precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0…
51 …precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0…
57 shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
60 shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
69 shrl.qb $3, $4, 5 # CHECK: shrl.qb $3, $4, 5 # encoding: [0x00,0x64,0xb8,0x7c]
70 shrlv.qb $3, $4, $5 # CHECK: shrlv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x55]
74 subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd]
[all …]
Dinvalid.s8 shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
9 shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
20 shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
21 shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
/external/llvm/test/MC/Disassembler/Mips/dspr2/
Dvalid.txt4 0x7c 0x04 0x18 0x52 # CHECK: absq_s.qb $3, $4
16 0x7c 0xe8 0x30 0x10 # CHECK: addu.qb $6, $7, $8
17 0x7d 0x4b 0x49 0x10 # CHECK: addu_s.qb $9, $10, $11
19 0x7e 0x11 0x78 0x18 # CHECK: adduh.qb $15, $16, $17
20 0x7e 0x74 0x90 0x98 # CHECK: adduh_r.qb $18, $19, $20
28 0x7c 0x64 0x16 0x11 # CHECK: cmpgdu.eq.qb $2, $3, $4
29 0x7c 0xc7 0x2e 0x51 # CHECK: cmpgdu.lt.qb $5, $6, $7
30 0x7d 0x2a 0x46 0x91 # CHECK: cmpgdu.le.qb $8, $9, $10
31 0x7d 0x8d 0x59 0x11 # CHECK: cmpgu.eq.qb $11, $12, $13
32 0x7d 0xf0 0x71 0x51 # CHECK: cmpgu.lt.qb $14, $15, $16
[all …]
/external/llvm/test/MC/Disassembler/Mips/micromips-dspr2/
Dvalid.txt4 0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
7 0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
9 0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
10 0x00 0xa4 0x19 0x4d # CHECK: adduh.qb $3, $4, $5
11 0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5
50 0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
61 0x00 0x62 0x08 0x6d # CHECK: precr.qb.ph $1, $2, $3
65 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
66 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
72 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
[all …]
/external/llvm/test/MC/Disassembler/Mips/dsp/
Dvalid.txt9 0x7c 0xe8 0x30 0x10 # CHECK: addu.qb $6, $7, $8
10 0x7d 0x4b 0x49 0x10 # CHECK: addu_s.qb $9, $10, $11
17 0x7d 0x8d 0x59 0x11 # CHECK: cmpgu.eq.qb $11, $12, $13
18 0x7d 0xf0 0x71 0x51 # CHECK: cmpgu.lt.qb $14, $15, $16
19 0x7e 0x53 0x89 0x91 # CHECK: cmpgu.le.qb $17, $18, $19
20 0x7e 0x95 0x00 0x11 # CHECK: cmpu.eq.qb $20, $21
21 0x7e 0xd7 0x00 0x51 # CHECK: cmpu.lt.qb $22, $23
22 0x7f 0x19 0x00 0x91 # CHECK: cmpu.le.qb $24, $25
81 0x7c 0x88 0x10 0xd1 # CHECK: pick.qb $2, $4, $8
93 0x7e 0x32 0x83 0x11 # CHECK: precrq.qb.ph $16, $17, $18
[all …]
/external/llvm/test/MC/Disassembler/Mips/micromips-dsp/
Dvalid.txt5 0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
6 0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
37 0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
49 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
50 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
56 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
59 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
68 0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
69 0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5
73 0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
[all …]
/external/llvm/lib/Target/Mips/
DMicroMipsDSPInstrInfo.td24 class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
25 class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>;
26 class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
27 class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
40 class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>;
50 class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>;
53 class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>;
56 class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>;
57 class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>;
62 class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>;
[all …]
DMipsDSPInstrInfo.td542 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
546 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
550 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
554 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
593 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
606 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
620 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
667 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
671 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
675 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
[all …]
/external/valgrind/none/tests/mips32/
Dmips32_dsp.stdout.exp-LE257 addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000
258 addu.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046138 DSPCtrl 0x00100000
259 addu.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000
260 addu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcc74 DSPCtrl 0x00100000
261 addu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000
262 addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335900 DSPCtrl 0x00100000
263 addu.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fef221 DSPCtrl 0x00100000
264 addu.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000
265 addu.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000
266 addu.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000
[all …]
Dmips32_dsp.stdout.exp-BE257 addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000
258 addu.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046138 DSPCtrl 0x00100000
259 addu.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000
260 addu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcc74 DSPCtrl 0x00100000
261 addu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000
262 addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335900 DSPCtrl 0x00100000
263 addu.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fef221 DSPCtrl 0x00100000
264 addu.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000
265 addu.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000
266 addu.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000
[all …]
/external/llvm/test/CodeGen/Mips/
Ddsp-r2.ll183 ; CHECK: cmpgdu.eq.qb
187 %2 = tail call i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8> %0, <4 x i8> %1)
191 declare i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8>, <4 x i8>) nounwind
195 ; CHECK: cmpgdu.lt.qb
199 %2 = tail call i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8> %0, <4 x i8> %1)
203 declare i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8>, <4 x i8>) nounwind
207 ; CHECK: cmpgdu.le.qb
211 %2 = tail call i32 @llvm.mips.cmpgdu.le.qb(<4 x i8> %0, <4 x i8> %1)
215 declare i32 @llvm.mips.cmpgdu.le.qb(<4 x i8>, <4 x i8>) nounwind
219 ; CHECK: precr.qb.ph
[all …]
Ddsp-r1.ll401 ; CHECK: addu.qb
405 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)
411 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
415 ; CHECK: addu_s.qb
419 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)
425 declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
467 ; CHECK: subu.qb
471 %2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1)
477 declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind
481 ; CHECK: subu_s.qb
[all …]
Ddsp-patterns-cmp-vselect.ll106 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
107 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
123 ; CHECK: cmpu.lt.qb $4, $5
124 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
140 ; CHECK: cmpu.le.qb $4, $5
141 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
157 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
158 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
174 ; CHECK: cmpu.le.qb $4, $5
175 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
[all …]
Ddsp-patterns.ll79 ; R1: addu.qb ${{[0-9]+}}
92 ; R1: subu.qb ${{[0-9]+}}
170 ; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
182 ; R1-NOT: shra.qb
184 ; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
196 ; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
224 ; R1-NOT: shll.qb
252 ; R1-NOT: shll.qb
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-dspr2.s9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
18 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
20 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
21 …adduh.qb $a1,$a1,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
22 …adduh_r.qb $a0,$9,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
28 …cmpgdu.eq.qb $s3,$zero,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
29 …cmpgdu.le.qb $v1,$15,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
30 …cmpgdu.lt.qb $s0,$gp,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
31 …cmpgu.eq.qb $14,$s6,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
32 …cmpgu.le.qb $9,$a3,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
Dinvalid-dsp.s14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
21 …cmpgu.eq.qb $14,$s6,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
22 …cmpgu.le.qb $9,$a3,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
23 …cmpgu.lt.qb $sp,$at,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
24 …cmpu.eq.qb $v0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
25 …cmpu.le.qb $s1,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
26 …cmpu.lt.qb $at,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
66 …pick.qb $11,$a0,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
76 …precrq.qb.ph $a2,$12,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]
/external/compiler-rt/lib/builtins/
Ddivtf3.c166 rep_t qb; in __divtf3() local
169 wideMultiply(quotient, bSignificand, &dummy, &qb); in __divtf3()
170 residual = (aSignificand << 113) - qb; in __divtf3()
174 wideMultiply(quotient, bSignificand, &dummy, &qb); in __divtf3()
175 residual = (aSignificand << 112) - qb; in __divtf3()
/external/libopus/celt/
Drate.c165 int qb; in compute_pulse_cache() local
199 qb = IMIN((num+(den>>1))/den, 57); in compute_pulse_cache()
200 celt_assert(qb >= 0); in compute_pulse_cache()
201 max_bits += qb; in compute_pulse_cache()
214 qb = IMIN((num+(den>>1))/den, (N==2?64:61)); in compute_pulse_cache()
215 celt_assert(qb >= 0); in compute_pulse_cache()
216 max_bits += qb; in compute_pulse_cache()
231 qb = IMIN((num+(den>>1))/den, MAX_FINE_BITS); in compute_pulse_cache()
232 celt_assert(qb >= 0); in compute_pulse_cache()
233 max_bits += C*qb<<BITRES; in compute_pulse_cache()
/external/chromium-trace/catapult/tracing/third_party/jszip/
Djszip.min.js13 …qb,a.adler=2===b.wrap?0:1,b.last_flush=H,D._tr_init(b),M):d(a,O)}function v(a){var b=u(a);return b…
14 …23,fb=24,gb=25,hb=26,ib=27,jb=28,kb=29,lb=30,mb=31,nb=32,ob=852,pb=592,qb=15,rb=qb,sb=!0;c.inflate…

123