Home
last modified time | relevance | path

Searched refs:r18 (Results 1 – 25 of 43) sorted by relevance

12

/external/libunwind/src/ia64/
DGinstall_cursor.S69 ld8 r18 = [r3], 2*LOC_SIZE // r18 = loc[IA64_REG_FR18]
80 and r18 = -4, r18
87 ldf.fill f18 = [r18] // f18 restored (don't touch no more)
169 ld8 r18 = [r2], (B5_LOC_OFF - B3_LOC_OFF) // r18 = b3_loc
181 and r18 = -4, r18
188 ld8 r18 = [r18] // r18 = *b3_loc
221 mov b3 = r18 // b3 restored (don't touch no more)
288 ld8 r18 = [r3] // r18 restored (don't touch no more)
DGresume.c50 unw_word_t r18; in local_resume() member
149 extra.r18 = c->eh_args[3]; in local_resume()
152 (long) extra.r17, (long) extra.r18); in local_resume()
Ducontext_i.h55 #define rB5 r18
/external/llvm/test/MC/Hexagon/
DasmMap.s29 #CHECK: 457fc012 { if (!p0) r18 = memuh(r31{{ *}}+{{ *}}#0)
30 if (!p0) r18=memuh(r31)
149 #CHECK: 3e1ec032 { memb(r30{{ *}}+{{ *}}#0) {{ *}}-={{ *}} r18
150 memb(r30)-=r18
233 #CHECK: 4312c801 if (p1.new) r1 = memb(r18{{ *}}+{{ *}}#0)
235 if (p1.new) r1=memb(r18)
283 p1=cmp.eq(r18,##1159699785)
341 #CHECK: 4692df01 if (!p1.new) memw(r18{{ *}}+{{ *}}#0) = r31
343 if (!p1.new) memw(r18)=r31
350 p2=cmp.eq(r18,##1895120239)
[all …]
Dv60-vmem.s50 #CHECK: 2992dd1f { if (q3) vmem(r18++#-3) = v31 }
52 if (q3) vmem(r18++#-3)=v31
225 #CHECK: 28b2c925 { if (!p1) vmem(r18+#1) = v5 }
227 if (!p1) vmem(r18+#1)=v5
294 #CHECK: 2b52c02c v12.cur = vmem(r18++m0):nt }
296 v12.cur=vmem(r18++m0):nt
/external/libunwind/tests/
Dia64-test-stack-asm.S45 alloc r18 = ar.pfs, 0, 0, 0, 0 // read ar.pfs
67 st8 [r3] = r18, (SAVED_BSP_OFF - SAVED_PFS_OFF)
71 mov r18 = ar.rnat
80 st8 [r3] = r18
106 ld8 r18 = [r3], (SAVED_RNAT_OFF-SAVED_PFS_OFF);; // saved pfs
112 mov ar.pfs = r18
Dia64-test-rbs-asm.S46 alloc r18 = ar.pfs, 2, (n)-2, 2, 0;/* read ar.pfs */ \
74 st8 [r3] = r18, (SAVED_BSP_OFF - SAVED_PFS_OFF); \
77 mov r18 = ar.rnat; \
87 st8 [r3] = r18; \
100 ld8 r18 = [r3], (SAVED_RNAT_OFF-SAVED_PFS_OFF);;/* saved pfs */ \
105 mov ar.pfs = r18; \
188 mov r18 = in1
220 mov in1 = r18
/external/valgrind/VEX/switchback/
Dtest_ppc_jm1.c145 register uint32_t r18 __asm__ ("r18");
3722 r18 = 0; in test_int_three_args()
3727 flags = r18; in test_int_three_args()
3729 xer = r18; in test_int_three_args()
3752 r18 = 0; in test_int_two_args()
3757 flags = r18; in test_int_two_args()
3759 xer = r18; in test_int_two_args()
3778 r18 = 0; in test_int_one_arg()
3785 flags = r18; in test_int_one_arg()
3787 xer = r18; in test_int_one_arg()
[all …]
/external/llvm/test/FileCheck/
Dsimple-var-capture.txt8 op3 r16, r18, r21
9 op4 r30, r18, r21
/external/llvm/test/Transforms/InstCombine/
Dfold-vector-zero.ll23 %r18 = add i64 %s0, %A
24 %r19 = inttoptr i64 %r18 to <2 x double>*
/external/llvm/test/CodeGen/PowerPC/
Dr31.ll6 …~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r2…
Daantidep-def-ec.mir58 '%r17', '%r18', '%r19', '%r20', '%r21', '%r22',
/external/compiler-rt/lib/tsan/rtl/
Dtsan_ppc_regs.h19 #define r18 18 macro
Dtsan_rtl_ppc64.S73 std r18,56(r3)
218 std r18,56(r3)
/external/valgrind/VEX/auxprogs/
Dgenoffsets.c213 GENOFFSET(MIPS32,mips32,r18); in foo()
250 GENOFFSET(MIPS64,mips64,r18); in foo()
287 GENOFFSET(TILEGX,tilegx,r18); in foo()
/external/llvm/test/MC/PowerPC/
Dppc64-regs.s23 #CHECK: .cfi_offset r18, 144
140 .cfi_offset r18,144
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td63 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
97 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
/external/valgrind/docs/internals/
Dregister-uses.txt151 r18 "Platform reg"
275 r18 n y
/external/v8/src/compiler/
Dc-linkage.cc117 r14.bit() | r15.bit() | r16.bit() | r17.bit() | r18.bit() | r19.bit() | \
/external/llvm/test/CodeGen/Mips/msa/
Dspill.ll93 %r18 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r17, <16 x i8> %18)
94 %r19 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r18, <16 x i8> %19)
242 %r18 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r17, <8 x i16> %18)
243 %r19 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r18, <8 x i16> %19)
391 %r18 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r17, <4 x i32> %18)
392 %r19 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r18, <4 x i32> %19)
540 %r18 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r17, <2 x i64> %18)
541 %r19 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r18, <2 x i64> %19)
/external/antlr/antlr-3.4/runtime/Python/tests/
Dt042ast.g94 r18
/external/llvm/test/CodeGen/X86/
D2007-01-13-StackPtrIndex.ll24 %r18 = sub i64 %r16, 0
25 %r19 = add i64 %r18, 0
27 %r19h = add i64 %r18, 0
/external/libunwind/doc/
Dunw_resume.tex44 handlers (e.g., IA-64 uses \texttt{r15}-\texttt{r18} for this
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILRegisterInfo.td40 def R18 : AMDILReg<18, "r18">, DwarfRegNum<[18]>;
/external/antlr/antlr-3.4/runtime/JavaScript/tests/functional/
Dt042ast.g100 r18

12