Home
last modified time | relevance | path

Searched refs:rcp (Results 1 – 25 of 33) sorted by relevance

12

/external/llvm/test/Transforms/InstCombine/
Dr600-intrinsics.ll3 declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
4 declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
9 %val = call float @llvm.AMDGPU.rcp.f32(float 1.0) nounwind readnone
16 %val = call double @llvm.AMDGPU.rcp.f64(double 1.0) nounwind readnone
23 %val = call float @llvm.AMDGPU.rcp.f32(float 0.5) nounwind readnone
30 %val = call double @llvm.AMDGPU.rcp.f64(double 0.5) nounwind readnone
35 ; CHECK-NEXT: call float @llvm.AMDGPU.rcp.f32(float 4.300000e+01)
37 %val = call float @llvm.AMDGPU.rcp.f32(float 4.300000e+01) nounwind readnone
42 ; CHECK-NEXT: call double @llvm.AMDGPU.rcp.f64(double 4.300000e+01)
44 %val = call double @llvm.AMDGPU.rcp.f64(double 4.300000e+01) nounwind readnone
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.rcp.f64.ll4 declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
10 %rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone
11 store double %rcp, double addrspace(1)* %out, align 8
18 %rcp = fdiv double 1.0, %src
19 store double %rcp, double addrspace(1)* %out, align 8
30 %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone
31 store double %rcp, double addrspace(1)* %out, align 8
Dllvm.AMDGPU.rcp.ll11 declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
12 declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
20 %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone
21 store float %rcp, float addrspace(1)* %out, align 4
34 %rcp = fdiv float 1.0, %src
35 store float %rcp, float addrspace(1)* %out, align 4
47 %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone
48 store float %rcp, float addrspace(1)* %out, align 4
Drsq.ll41 ; Recognize that this is rsqrt(a) * rcp(b) * c,
42 ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
/external/deqp/framework/delibs/debase/
DdeInt32Test.c47 deUint32 rcp = (deUint32)((1u << DE_RCP_FRAC_BITS) / ((double)val / (1<<RCP_LUT_BITS))); in deInt32_computeLUTs() local
52 printf("0x%08x", rcp); in deInt32_computeLUTs()
72 deUint32 rcp; in deInt32_selfTest() local
133 deRcp32(val, &rcp, &exp); in deInt32_selfTest()
135 DE_TEST_ASSERT(rcp == (1u<<DE_RCP_FRAC_BITS)); in deInt32_selfTest()
152 deRcp32(val, &rcp, &exp); in deInt32_selfTest()
154 DE_TEST_ASSERT(rcp >= ref-EPS && rcp < ref+EPS); in deInt32_selfTest()
DdeInt32.c78 void deRcp32 (deUint32 a, deUint32* rcp, int* exp) in deRcp32() argument
173 *rcp = result; in deRcp32()
DdeInt32.h39 void deRcp32 (deUint32 a, deUint32* rcp, int* exp);
/external/libopus/celt/
Dmathops.c71 opus_val16 rcp; in frac_div32() local
77 rcp = ROUND16(celt_rcp(ROUND16(b,16)),3); in frac_div32()
78 result = MULT16_32_Q15(rcp, a); in frac_div32()
80 result = ADD32(result, SHL32(MULT16_32_Q15(rcp, rem),2)); in frac_div32()
Dvq.c201 opus_val16 rcp; in alg_quant() local
221 rcp = EXTRACT16(MULT16_32_Q16(K-1, celt_rcp(sum))); in alg_quant()
225 iy[j] = MULT16_16_Q15(X[j],rcp); in alg_quant()
227 iy[j] = (int)floor(rcp*X[j]); in alg_quant()
/external/llvm/test/CodeGen/X86/
D2008-05-22-FoldUnalignedLoad.ll6 %inv = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %tmp2)
17 declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
D2013-03-13-VEX-DestReg.ll18 %1 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecinit4.i.i) #2
24 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) #1
Dfold-load-unops.ll19 %res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ins)
76 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
Dsse-scalar-fp-arith-unary.ll20 %y = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %x)
70 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>)
Dsse-intrinsics-x86.ll181 %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
184 declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
189 %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
192 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
Dsse_partial_update.ll41 %0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind
49 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
Dsse_reload_fold.ll14 declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
51 %t = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %f)
/external/dnsmasq/contrib/dns-loc/
Ddnsmasq2-loc-rfc1876.patch426 + register const u_char *rcp;
441 + rcp = binary;
448 + versionval = *rcp++;
455 + sizeval = *rcp++;
457 + hpval = *rcp++;
458 + vpval = *rcp++;
460 + GETLONG(templ,rcp);
463 + GETLONG(templ,rcp);
466 + GETLONG(templ,rcp);
/external/mksh/src/
Dedit.c3116 char *rcp, *cp; in x_prev_histword() local
3139 rcp = &cp[strlen(cp) - 1]; in x_prev_histword()
3143 while (rcp > cp && is_cfs(*rcp)) in x_prev_histword()
3144 rcp--; in x_prev_histword()
3145 while (rcp > cp && !is_cfs(*rcp)) in x_prev_histword()
3146 rcp--; in x_prev_histword()
3147 if (is_cfs(*rcp)) in x_prev_histword()
3148 rcp++; in x_prev_histword()
3149 x_ins(rcp); in x_prev_histword()
3154 rcp = cp; in x_prev_histword()
[all …]
/external/clang/test/CodeGenOpenCL/
Dbuiltins-r600.cl76 // CHECK: call float @llvm.AMDGPU.rcp.f32
83 // CHECK: call double @llvm.AMDGPU.rcp.f64
/external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/defs/
Dopcodes.txt130 rcp
/external/pdfium/fpdfsdk/src/pdfwindow/
DPWL_Note.cpp1259 PWL_CREATEPARAM rcp = cp; in CreateChildWnd() local
1260 rcp.pParentWnd = this; in CreateChildWnd()
1261 rcp.dwFlags = PWS_VISIBLE | PWS_CHILD; in CreateChildWnd()
1262 rcp.eCursorType = FXCT_NWSE; in CreateChildWnd()
1263 rcp.sTextColor = sTextColor; in CreateChildWnd()
1264 m_pRBBox->Create(rcp); in CreateChildWnd()
/external/llvm/test/CodeGen/PowerPC/
Drecipest.ll114 ; Recognize that this is rsqrt(a) * rcp(b) * c,
115 ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_peephole.cpp1082 AlgebraicOpt::handleRCP(Instruction *rcp) in handleRCP() argument
1084 Instruction *si = rcp->getSrc(0)->getUniqueInsn(); in handleRCP()
1087 Modifier mod = rcp->src(0).mod * si->src(0).mod; in handleRCP()
1088 rcp->op = mod.getOp(); in handleRCP()
1089 rcp->setSrc(0, si->getSrc(0)); in handleRCP()
Dnv50_ir_lowering_nv50.cpp954 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1)); in handleDIV() local
956 i->setSrc(1, rcp->getDef(0)); in handleDIV()
/external/mesa3d/src/gallium/drivers/nvc0/codegen/
Dnv50_ir_lowering_nvc0.cpp939 Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1)); in handleDIV() local
941 i->setSrc(1, rcp->getDef(0)); in handleDIV()

12